Release Version 2025.8.6.1

Changelog

All notable changes to this project will be documented in this file.

[2025.8.06.1]

New Features

  • DIG2 USB Connection
    • Introduced USB Connection String configuration for DIG2 boards.
  • Clock Domain Crossing (CDC)
    • Added single-bit CDC block for Altera FPGAs.
    • Added multi-clock CDC support for V2495 to handle multiple clocks in the same project.
  • New IP Blocks
    • CFD (Constant Fraction Discriminator) block for TM signals, with example for V2730.
    • New synchronous SET-RESET FLIP-FLOP block.
  • Project Versioning
    • Automatic versioning with support for formats:
      • YYYY.MM.DD.XX
      • A.B.C.D
      • simple incremented values.
  • Link Checker & Signal Types
    • Introduced new strategy for link checking:
      • Link turns red if the anchor point type doesn’t match the connected signal.
    • New color-coded anchor points:
      • Orange (TM), Azure (BIT VECTOR), Green (INTEGER), Yellow (BIT)
  • Backward Compatibility Warning
    • Display warning when opening projects saved with older Sci-Compiler versions.
  • Documentation & Examples
    • Added documentation on:
      • QDC and Trigger Leading Edge.
      • TM IP usage on V273X.
    • New user guides for:
      • CONST FIXED POINT, CONST TIME, ARRAY CROSS CLOCK, DELAY SINGLE, DSP - ACCUMULATOR
      • COMMENT, OSC AVG, OSC DUAL, OSC TM, TDC SYNCHRONOUS, CFD-D, TDC 500 PS
      • RISE TIME, PEAK DETECTOR, PEAK TM, MIN DETECTOR, TRP MCA, PILEUP REJECT, PUR SIMPLE

Improvements

  • Pre-Compiling Speed
    • Achieved up to 10x faster pre-compiling times.
  • Automatic IP Upgrade
    • All IPs are auto-updated when design or user guide is modified in the new release.
  • Stimulus File and Constant Checks
    • Verifies values in CONST blocks.
    • Checks existence of files used in FILE and GENERATOR blocks.
  • Oscilloscope Dual/AVG
    • Now functional without requiring digital I/O.
  • Moving Average Block
    • Rewritten using HLS with extended configuration options.

Bug Fixes

  • Variable Size Blocks
    • Fixed broken links when updating components with variable sizes.
  • CUP Generator
    • Fixed logic issue in the CUP firmware generator.
  • TM Pin Type Mismatch
    • Corrected signal type for TM pin in Derivative Trigger block.
  • LEFT SHIFT block
    • Fixed incorrect behavior of LEFT SHIFT block with same-sized inputs.
  • Memory Blocks
    • Fixed memory sizing bugs in DPRAM and SPRAM.
  • Derivative Trigger TM
    • Resolved logic errors affecting TM trigger condition.
  • Compilation Errors
    • Removed false error messages during compilation on V27XX boards.
  • FIFO block
    • Fixed FIFO block issue that caused crashes.
  • ONE-FILL Block
    • Resolved malfunction during operation.
  • Labeling Issues
    • Corrected label on TM polarity inverter (previously mislabelled as “invert polarity”).
  • Signal Naming Consistency
    • Unified naming between QDC and QDC TM blocks.
  • Simulation Support
    • Global Reset signal now correctly driven in simulation for X2730 and X274X boards.

[2025.6.18.1]

New Features

  • TRP Trapezoidal PHA
    • Added new TRP Trapezoidal PHA block with improved performance for Transistor Reset PHA.
    • Support for leakage current compensation in TRP PHA.
  • Oscilloscopes
    • Support for longer oscilloscopes.
  • New IP for Time Multiplexed Board (V2730)
    • PSD
    • Fix QDC
    • Derivative Trigger
  • New advanced pileup rejection
    • Added advanced pileup rejection block with capabilities to discard single and double pileup events.
    • Simple pileup rejection block for basic functionality.
  • Framework Lite
    • CAEN board now supports a lightweight framework for faster compilation (V27XX).

Bug Fixes

  • License Management
    • Fixed enterprise license bug preventing proper dongle write/refresh.
    • Corrected license crash in Chinese patch.
  • Simulation & HLS
    • Fixed “list simulation” and “freq meter sim” display issues.
    • Fixed HLS bug in certain blocks to enable remote compilation.
    • Removed top pragma from PUR for HLS 2027 compatibility and added debug info to logs.
  • Triggers & I/O
    • Corrected I/O trigger on DT5550W.
    • Fixed User TRIGGER and USER_RUN
  • Component Fixes
    • Renamed Citiroc2UI to CitirocUI.
    • Fixed ISCIPLUGIN override that was overwriting ComponentInfo.
  • Resource Explorer
    • Fixed table not saving unless entries made in “Value Write” column
    • Fixed 32-bit oscilloscope bug.
  • Fixed baseline drift issue
    • Corrected offset between prohibited words.
  • UI
    • Resolved “Generate project only” compile mode hang
    • Resolved progress bar issues during plugin loading.
    • Removed top from pileuprejector.
  • Pattern Generator
    • Fixed Altera pattern generator.
  • List Bug Fix
    • Added a wordsize parameter in lists in json.
  • Other Fixes
    • Fixed help and on-screen documentation.
    • Corrected QDC PSD and PSD TM bugs.
    • Fixed enable fixed time check and port names in QDC TM.

Improvements

  • Examples & Documentation
    • Updated CAEN board examples
    • Corrected TM block guide and spectrum bit-size documentation.
  • CI/CD & Pipeline
    • CAEN Framework upgraded to v1.6.3 for X27XX.
  • Logging & Tracing
    • Introduced notrace option to disable intensive tracing.

[2025.3.20.1]

New Features

  • Examples for CAEN boards

  • Reset in simulation (for DT1260)

  • Timer Start/Stop new parameters to restart timer on start signal after stop

  • License Dematerialization & Management

    • Added support for converting dongle licenses into digital licenses, including OTP recovery.
    • Implemented temporary relocation of digital licenses to USB dongles and back.
    • Enabled managing multiple dongles simultaneously, with improved UI feedback.

  • FPGA Plugin Architecture

    • Ported/Created New Blocks as Plugins:
      • Counters, Frequency Meter, Scaler, Round Robin, Majority Trigger, Double Trigger
      • Pattern Generator, Sequence Logic, BL Restorer, Peak Holder, Min Holder, Energy Sampler
      • Bitwise Operations (bit-slice, fill, sign extension), Wire Merge/Split, Mux
      • Single-Clock Delay, Constant (True/False/Float), Adder, Subtractor, Accumulator, Programmable Shift (Left/Right)
      • “bin to int” / “int to bin” converters

  • New Digitizer Support (DT5571)

    • Added DT5571 Digitizer plugin/component.
    • Integrated resource explorer entries (e.g., ring DDR buffer size, plotting threshold).
    • Provided an example project demonstrating digitizer usage.

  • Simulation & Remote Compilation

    • Introduced VHDL-based builds for certain HLS blocks (migrated from DCP).
    • Added specialized examples for newly ported FPGA blocks.

  • Progress Bar & UI Overhaul

    • Progress Bar now indicates plugin loading status during application startup.
    • Simplified UI by removing legacy or unused buttons (e.g., float/timer controls).
    • Enhanced menu organization and introduced tabbed layouts in critical dialogs.

Bug Fixes

  • Dongle & License Management

    • Fixed writing/activation bugs on USB dongles (preventing partial/corrupted license writes).
    • Corrected issues when transferring licenses to a dongle after a previous transfer had expired.
    • Resolved a bug where a license appeared “in use” incorrectly.
    • Fixed UI refresh problems in the License Manager when dongles were disconnected or reconnected.
    • Improved error messages for trial-license errors and user-not-logged-in scenarios.
    • Support for conversion of dongle licenses to digital licenses.
    • Support for temporary relocation of a digital license to USB dongle.

  • FPGA & HLS-Related Fixes

    • RAM FIFO: Fixed initialization and removed legacy code.
    • Clock & Timing:
      • Addressed extra 1-cycle delay errors in multiple modules.
      • Fixed DT5571 DAC clock phase issue and removed the need for external data latch.
      • Corrected default rising/falling edges on HLS-based blocks.
    • Subpage Simulation: Patched issues that caused invalid intermediate files and inconsistent runs.
    • Spectrum & Charge Integration:
      • Resolved calculation errors in charge integrator blocks.
      • Fixed spectrum simulation to properly handle parameter limits.
    • Bitwise & Double Signal Conflicts: Eliminated duplicate or ghost signals in netlists.

  • UI & Stability

    • Fixed out-of-range or non-existent port references (e.g., TE trigger block).
    • Ensured .NET exception handling for erroneous project files (e.g., invalid simulation inputs).
    • Addressed tabbed layout bugs in the main interface and certain pop-up dialogs.

Improvements

  • Authentication & HTTP Requests

    • Implemented an automatic token refresh for HTTP interactions when nearing expiry.

  • Remote Compilation & CAEN Frameworks

    • Automated the upgrade to CAEN framework v1.5.0 for X27XX boards.
    • Added internal scripts that update and replace frameworks for remote builds, removing absolute paths.

  • Digitizer Refinements

    • Introduced ringDDR buffer size checks (read_size > 0) to enable automated plotting.
    • Removed temporary debugging patches once digitizer stability was confirmed.

  • Resource Explorer & Example Projects

    • Provided new example designs for X27XX boards and the DT5571 digitizer.
    • Added help links and short documentation for newly ported components.

  • Installation & Build Process

    • Improved Inno Setup configuration, including naming of generated executables and artifact paths.
    • Streamlined build scripts for local/remote compilation and automatic CAEN library updates.

[2024.10.30.1]

  • Updated frameworks for X27XX family.
  • Fixed a bug in the Moving Average block.

[2024.10.15.1]

  • Fixed bug on generated firmware for X27XX family.
  • Fixed bug on local compilation for X2730 Wave.
  • Improvements in login process.

[2024.10.9.1]

  • Migrated personal area from caen.it to my.sci-compiler.com
  • Support for digital licenses.
  • Built in firmware versioning system.
  • Remote builds for all supported boards.
  • Remote simulation for all supported boards.

[2024.9.11.3]

  • Support to offline compiler for all boards of X27 family
  • Rolling average and variance
  • Full (Fractional scaler)
  • Fix missing files on Citiroc/Petiroc board
  • Updated user guide of scaler and gate and delay

[2024.7.19.1]

  • Altera pll component to generate clock

[2024.6.4.1]

  • xlx_delay memory bug fix
  • x2730 online compile
  • updated user guide for Charge integration and patter generation
  • reset and clock signal type to std_logic_vector for legacy charge integrator
  • removed offline compile file for CAEN boards
  • fixed bug position for peak finder
  • SciSDK 1.2.58 with fixed caen libCAEN_FELib.so

[2024.5.4.1]

  • Fixed cup generator

[2024.4.25.1]

  • Support to 10Gbps UDP on v27xx digitizer

[2024.4.2.2]

  • Fixed incorrect management of extra license plugins/boards

[2024.4.2.1]

  • Fixed missing welcome page

[2024.4.1.1]

  • Fixed mixed file in the setup

[2024.3.27.1]

  • Hide unlicensed plugins and boards

[2024.3.26.1]

  • Fixed bug on autosize of subpage memory area < 512 bytes

[2024.3.19.1]

  • Custom Packet for V2495
  • Max delay of software GD can be selected at compile time

[2024.2.28.1]

  • Menu on right click of the three and double click to open page.
  • Fixed point constant component
  • Added new IIR Butterworth, Bessel, Chebyshev I, Chebyshev II, Elliptic, Notch and Resonant second order filter
  • Added new IIR Butterworth and Bessel first order IIR filter
  • Added new IIR first and Second order IIR filters using scattered look-ahead tecnique
  • Fixed rate meter memory region area
  • New hierarchical RegisterFile Json (for future version of SciSDK)
  • Readout element inside subpage (MR !18)
  • Magic Number in JSON RegisterFile to identify the firmware

[2024.1.22.1]

  • ESS upgraded framework

[2024.1.6.1]

  • Vivado cpu usage calculated in function of the number of core available. 4 up to 4 core, N-2 for more than 4 core
  • DMA working on all family x5560x
  • FLags lines are now available on R5560SE
  • Fixed bug MAGIC not written in in json file

[2023.12.8.1]

  • Add 32 bit word size to list
  • Fixed x2730 x2740 library bug prevent access address > 0xffff

[2023.11.29.1]

  • Fixed bug list on V2495
  • Fixed bug remote compilation with HLS on X27XX
  • Fixed bug on DPP list wave input when input is not connected
  • Updated CAENFee Libs
  • Updated V2495 old examples
  • Fixed bug on HW Gate and Delay on V2495
  • Fixed bug on create constant (size was always 8 bit)
  • Fixed bug on ALT+R Shortcut
  • New examples for DT5771 and V2730

[2023.11.15.1]

  • Fixed bug crash software when create example
  • Fixed old V2495 old example (SciCompiler 2018)
  • Fixed bug crash software open some old project
  • Fixed missing ip core NIDNA in R5560-Minimal image
  • Fixed all bug in CustomHLD (missing TM, typo in template)
  • In CustomHDL automatic replace template name with module name. Just leave and save
  • Fixed bug in converting hex number in integer constant
  • Add code examples using Time Multiplexer for x2730
  • Fixed alt_list missing generic port
  • Fixed ALT+R Shortcut bug
  • Fixed bug setting wrong size in constant created from right click in-place menu
  • Add full MCA with QDC, PHA, PSD, CFD, ToF, timetag example for DT5771

[2023.10.18.1]

  • Fixed files framework for offline compilation of x2730
  • Buf fix on histeresys of ToT
  • Display and key support for DT5771

[2023.10.12.1]

  • Add support to V2730 (MR !17)
  • Updated DT555X library
  • GlobalClock to DT5571 framework
  • PSD enable property fix bug

[2023.9.22.1]

  • Patch Vivado < 2022 with Y2K patch

[2023.9.15.2]

  • Install report tool in Vivado

[2023.9.11.2]

  • Official support for DT5771 (MR !16)

[2023.9.10.2]

  • Missing block diagram file for offline and online compiler patched
  • Min/Max block bug corrected
  • Unconnected pin in subdesign bug corrected
  • Code factoring (MR !15)

[2023.8.10.1]

  • All register can be read and write, include register file
  • Register write only (as well as mmc endpoint internal register) now can be also read (MR !14)

[2023.8.8.1]

  • Support to HLS cores (this will allows to implement several new fetures and cores in next editions)
  • Support to DT5771
  • Removed autosave feature
  • Fixed visibility of board compatible toolbox elements managing the board restrictions
  • New organization of toolbar elements
  • Improved Charge Integration and PSD
  • Improved Trapezoidal PHA chain
  • Measure of rise time example
  • New oscilloscope component with gated average decimation
  • New oscilloscope component dual with gated average decimation
  • New oscilloscope component with 16/24/28 input width support
  • Fixed resource explorer to display chart in samples and not in incoerent time
  • Fixed resource explorer to display the decimation factor in absolute number
  • Fixed SciCompiler bug make it crash without internet connection
  • Fixed resource explorer to display signed number in oscilloscope

[2023.7.28.1]

  • Ask to save on exit

[2023.7.26.1]

  • Hidden I/O not compatible with the selected board. Applied to toolbar and quick menu

[2023.7.25.3]

  • Bug fixed on register compiling. During save, register addresses were reset to 0.
  • Rise time of a signal measurament using R5560 (example)

[2023.7.25.2]

  • Bug in log4net resource explorer

[2023.7.25.1]

  • Better log on License Manager
  • R5560-A dcp missing

[2023.7.24.2]

  • Updated ESS to Vivado 2022.2

[2023.7.24.1]

  • Bug on missing registers in memory mapped list solved

[2023.7.21.1]

  • On project open SciCompiler will lock for missing linked files and ask user to provide the new path
  • Lemo on DT5560
  • Updated Caen Lib
  • Bug on data type for variable. Not working with integer (MR !11)
  • Peak finder hdl bug (MR !10)
  • Add custom notes to top page and sub pages (MR !9)
  • Hierarchical Tree for subdesign

[2023.7.20.1]

  • Log in resource explorer

[2023.7.18.1]

  • Error in project link for Petiroc components
  • Resource Explorer is protected agaist missing board libraries

[2023.7.14.1]

  • Add EULA to setup (MR !7)
  • Added log features to license and cloud (MR !6)
  • Added CI/CD automatic upload on the new Sci-Compiler site https://www.sci-compiler.com (MR !5)
  • Shortcut to create registers and port
  • MCA fast
  • Transistor reset processing chain

[2023.03.13.1] - Viareggio Edition

  • (1) Offline compile for X2740-DPP
  • (5) Bug on Resource Explorer list read out more data than available

[2023.02.28.1] - Viareggio Edition

  • (1) New ess DRGO core

[2023.02.10.2] - Viareggio Edition

  • (1) Support for R5560SE
  • (1) Re-target for different hardware
  • (5) Bug on tof spectrum patched, no more dead-time between bins
  • (1) Switched to Sci-SDK library
  • (1) Official Support for remote compile
  • (1) Simulation for all board except DT5550W and V2495

[2022.11.0.3] - Bellagio Edition

  • (5) Simulation, missing dll in setup make unusable the register script editor
  • (1) DT1260 support remote customization service
  • (1) DT5560/R5560-A/R5560-A-SE support remote customization service
  • (1) X274X Dpp mode, Global software RUN enable and disable all DPP output LIST from software
  • (1) X274X Dpp mode, Software enable control each DPP enable signal LIST
  • (1) Support to the new BETA library SciSDK: https://github.com/NuclearInstruments/SCISDK

[2022.11.0.1] - Bellagio Edition

  • (1) Simulation, for now supported for DT1260 only and in local
  • (5) Solved bug on trigger for frame readout
  • (5) Solved bug on spectrum, the running flag never go back to zero after a start

[2022.9.0.5] - Bellagio Edition

  • (5) Bug in Image Transfer prevent external trigger to be selected from SDK

[2022.9.0.4] - Bellagio Edition

  • (1) Support for V2740 DT2740 V2745 DT2745
  • (1) Cloud compiling feature for X274X boards
  • (1) Migrated my.scicompiler.cloud on MyCAEN+
  • (1) Support for trial license
  • (1) Support for viewer only mode
  • (1) New license manager with integrated MyCAEN interface for dongle and trial license management
  • (1) Support to the new R5560 architecture with better integration between base and DAQ
  • (1) (R5560/R5560SE) Flag signal connect adjacent DAQ in order to allow fast trigger or synchronization between DAQ
  • (1) Flag signal example to make H-LINK delay deterministic (see AN https://www.sci-compiler.com/application-notes/013-r5560-horizontal-interconnections/)
  • (5) R5560SE DAQ clock is now provided from the BASE and acquisition of all DAQ are synchronous
  • (1) Removed limit of 64K samples per oscilloscope. Now oscilloscope can use all the available memory
  • (1) User Guide for X2740/5 DPP/Wave readout block
  • (5) Updated DT1260(SCIDK) sdk library. Missing ReadFIFO
  • (5) Bug in the framework of DT1260 read an extra work corrected. At the end of a FIFO readout it causes a missed word in long packet
  • (1) Possibility to install and run SciCompiler even without any locally installed Vivado or Quartus
  • (5) Bug on digitizer IP prevent a correct online data decoding in Resource Explorer with more than 2 channels