This example measures both Time over Threshold (ToT) for an analog signal and a Timestamp associated with each event. The design then stores (or “lists”) these measurements in a memory buffer for later readout.

1. Diagram Overview

Below is the core schematic:

Key blocks and signals:

1. Analog Input Pin (A0)

   • Receives the analog signal whose time and duration we want to measure.
   • For instance, a pulse from an external source or a test generator.

2. Trigger LE Hyst

   • Generates two main outputs from the analog signal:
     • TRIGGER: Goes high when the input crosses the threshold on a leading edge.
     • TOT: Remains high for as long as the input is above the threshold (time over threshold).
   • Threshold and polarity settings come from registers:
     • THRESHOLD (16 bits)
     • POLARITY (1 bit)
     • DELTA (additional hysteresis, optional)

3. Timestamp Block

   • A dedicated module that produces a 32‐bit TIMETAG and resets on T0.

4. Edge Detectors (FALLING)

   • Edge Det. FALL is connected to the TOT signals, capturing the moment the TOT ends.
   • These pulses typically feed logic that commits data (like time stamps or counters) to memory.

5. Chrono (Enable)

   • Another time-measurement block that can be started/stopped to measure intervals.
   • For instance, it measures the time from the rising to the falling of the TOT

6. D Latch, Wire Merge

   • The design shows a D Latch storing the 32‐bit time tag from Timestamp (for example, on a rising edge).
   • A Wire Merge might combine two 32‐bit words (e.g., TOT time and TIMETAG) into a single 64‐bit data word.

7. List_0 (List Block)

   • Receives 64‐bit event data (IN) and a Write Enable (WE, or WR) signal.
   • When an event occurs, the logic asserts WR=1, storing that 64‐bit data in an internal buffer.
   • We can accumulate many events without involving the PC for each one.
   • The List block’s BUSY output indicates it’s transferring data out, and FULL indicates no more memory is available.

8. REG: RUN and Edge Det. RISE → RunPulse

   • A register bit that the user can set to 1 in software.
   • The rising edge of this signal is turned into a short pulse (e.g., RunPulse) that might enable the Chrono, or clear counters, or generally start the measurement run.

9. Pulse Generator (PWM) + LEMO_0

   • Provides a test signal if needed. In this diagram, it’s set up so a user can generate a pulse output on the front panel.
   • Alternatively, one might feed an external signal into LEMO_0 for synchronization or triggers.

10. Oscilloscope

    • Monitors key signals (AnalogSignal, Trigger, Tot, Commit, Run) to debug timing and verify the logic.

2. Role of the “List” Block

The List block in Sci-Compiler is a memory buffer for event‐by‐event data.

• IN (width 64 bits here) is the data to store (timestamp, TOT, other relevant fields).
• WR is asserted when the system wants to record a new event into the list.
• CLK is usually the system clock (e.g., 65 MHz).
• RESET clears the entire buffer.
• BUSY means data is being transferred out (e.g., when you read from the block).
• FULL means the buffer is at capacity and can’t store new events.

Downloading the Data

Once events have been stored:

1. Enable readout by writing the appropriate bits to CONFIG (e.g., "10").
2. Check if not empty (STATUS).
3. Use the SciSDK or Resource Explorer to read from the List Address.
   • You specify how many data words you want.
   • The block streams out the stored 64-bit events.

3. Use Case in This Design

1. An event occurs when the analog input crosses the threshold. The TOT block stays high until the pulse goes back below threshold.
2. Timestamp or Chrono is latched so we know when the event happened or how long TOT lasted.
3. At the end of the event (or the beginning, depending on the logic), the 64‐bit data (e.g., [Timestamp, TOT_duration]) merges into the List input, and we assert WR=1 for one clock to store that event in the list.
4. Software eventually reads the entire list, retrieving a time‐tag/TOT pair for each event.
5. The user can process or analyze these event records offline (for example, building histograms or correlating TOT with arrival time).

4. Summary of Operation

• Threshold crossing → generates TRIGGER and TOT signals.
• Timestamp and Chrono block → captures the time and TOT.
• Edge detectors → identify specific transitions (rising/falling) to store data.
• Wire Merge + List → pack the 32-bit time and TOT into a 64-bit event, store in memory.
• REG RUN → software starts the acquisition.
• Oscilloscope → real‐time check of signals.
• List → read out in Resource Explorer or SciSDK as a binary data stream once the measurement run is complete.

With this design, you can record discrete event data (timestamp + TOT) in a buffer on the FPGA, then download it for offline or real‐time analysis, while monitoring all signals on the built‐in oscilloscope for debugging.

Readout using Resource Explorer

In this lab, we configure the DT1260 firmware (which includes trigger, ToT, and list blocks) to save raw data to a file via the Resource Explorer. Then we examine the binary file with a hex editor (HXD) to observe the recorded words (e.g., ToT, ToF, etc.).

1. Register Setup

1. Open Resource Explorer → Registers

   • THRESHOLD = 2300 (or as needed to ensure the analog signal crosses threshold)
   • PULSE_PERIOD = 1000, PULSE_WIDTH = 50 (if you’re using an internal PWM generator as a test source)
   • RUN = 0 initially (stopped)

2. Press “Set All” to write the desired register values to the board.

   

2. Running the Firmware

1. Set RUN = 1 (in the register table) to start the data acquisition logic.
2. Check the Oscilloscope in the Resource Explorer:
   • You can see trigger signals, ToT pulses, or other lines.
   • If the trigger or ToT signals are missing or the threshold is incorrect, adjust the THRESHOLD register accordingly.

3. Configuring the List Block for File Output

1. In Resource Explorer, under Lists (or a similarly named node), find your list block (e.g., List_0).
2. Right-click → Download to open the Download window.
3. File Name: Provide a name (e.g., lab10).
4. File Folder: Choose a path (e.g., c:\temp\).
5. Target Size: You might specify “10 kW” meaning 10 kWords ( 40 kB, each word is 4 bytes).
6. Packet Size: e.g. 128 word.

Format: Set to Raw for a straightforward binary file.

Start the acquisition to begin recording the raw data streaming from the list block.

4. Inspecting the Binary File

1. After the acquisition reaches the Target Size or you manually Stop, you’ll have a file like c:\temp\lab10.bin.
2. Open it in a hex editor, such as HxD.
3. You’ll see pairs of bytes (or 32-bit words, depending on how your firmware outputs data). For example:
   • The ToT field might be the first 4 bytes.
   • The ToF field might be the next 4 bytes.
   • In your test, if no T0 is applied, the ToF might continuously increment or be zero. The ToT might remain constant if your input signal has stable amplitude.

Example Observations:

• ToT: The first 4 bytes remain a constant pattern for every event if the pulse amplitude/width is unchanged.
• ToF: If no T0 is present, it might be changing or some default. If there were a T0, you’d see these bytes vary based on the actual flight time.

Hex Data with signal pulse width of 600ns

Hex Data with signal pulse width of 1680ns