Sci-Compiler

In this lab, we demonstrate how to acquire and read out data from multiple input channels in a Round Robin fashion using a FIFO-based arbiter. We then show how to retrieve the recorded data via the Resource Explorer and finally interpret (decode) the binary files with an external hexadecimal editor such as HxD.

1. Introduction

When multiple channels produce data at the same time (or nearly so), we need a way to “arbitrate” access to a shared resource—in our case, a FIFO (First-In-First-Out) memory or output bus. A Round Robin Arbiter ensures that each channel gets its turn in a fair, time-shared manner. Each channel can write to the FIFO in a “round robin” cycle so that no single channel monopolizes the resource.

1.1 What the Arbiter Does

The Round Robin FIFO Arbiter block implements an algorithm commonly used in scheduling:

Round Robin scheduling gives each requestor/channel a time slot to submit data.
If a channel becomes inactive or completes transmission, the arbiter moves on to the next channel.
The design is “work-conserving”: it skips inactive channels to avoid wasting time.
Internally, a small FIFO structure queues active channels in the order they request service.

In simpler terms, if multiple channels have data, the Arbiter takes one data word from each channel in turn, then cycles back to the first channel again if it still has more data.

2. Block Diagram Overview

Below is a high-level diagram of the processing chain. Each colored block represents a functional module in the firmware design (e.g., for signal triggering, baseline restoration, QDC integration, etc.). The final stage is the Arbiter RR FIFO (in red), which combines outputs from multiple upstream blocks before writing to the List block in memory.

Here is a brief description of each notable block:

Analog PIN
- Physical analog input channel(s). Each channel enters the digital logic via an ADC or a front-end.
Const Bit-Vector (various small blocks feeding threshold or configuration values)
- These constant blocks feed fixed integer (bit-vector) parameters to other blocks. Examples include numeric constants for thresholds, gain, or dwell times.
Trigger LE H (U3 and U4)
- Two trigger blocks that detect leading-edge triggers based on a configured threshold.
- DATA IN: The 16-bit digitized signal from the ADC.
- THRESHO: The threshold input.
- TRIGGER OUT: A 1-bit trigger indicating when the input crosses that threshold.
Baseline Restore (U5 and U8)
- Removes or estimates the baseline (pedestal) level of the input signal.
- DATA IN: The raw or partially processed ADC data.
- BASELINE: The restored baseline value, useful for offset correction.
- DATA OUT: The corrected signal.
QDC (U12 and U13)
- “Charge-to-Digital Converter” blocks integrate or sum the pulse over a certain time window to measure its “area” (charge).
- TRIGGER: Start integration when trigger is detected.
- CHARGE: Output integrated charge value.
- ADDR, BUSY, etc.: Various handshake signals.
REG (U7, U14, U16)
- Simple register blocks holding user-defined parameters such as DWELL (acquisition window length), GAIN factors, or other calibration settings.
Timestamp (U19)
- Generates or captures time information (optional).
- T0 / T0H: Lower/higher bits of time stamp.
Wire Merge (U18, U20)
- Combines multiple lines of data or signals into a single bus to great a data packet.
Data packet format:
- QDC: 16 bit charge value.
- TIMESTAMP: 48 bit timestamp value.
Arbiter RR FIFO (U17)
- The Round Robin FIFO Arbiter. It takes multiple inputs (each accompanied by a “Data Valid” or DV signal) and grants them access to the single output bus in a round-robin order.
- Output includes:
  - DATA (the selected channel’s data),
  - ADDRESS (the channel ID or address),
  - A+D (a combined bus with both address and data),
  - DV (Data Valid),
  - BUSY (signals back to the source that the Arbiter is processing the channel).
List (U21)
- A FIFO-based list or memory storage block. Data from the Arbiter is written sequentially into a buffer that can be read later by software (Resource Explorer).
- IN0 / WE: Data input and write-enable.
- FULL: Status indicator.
- CLK / RUNNING: Clock and run signals controlling when data is written.
- RESET: Clears the list FIFO.
Oscilloscope (U2)
- A built-in logic oscilloscope for real-time inspection of waveforms. In the screenshot, it is used to show the raw pulse (Channel 1) and additional signals (Channel 2, etc.). Overall, the flow is: Analog Input → Trigger → Baseline Restoration → QDC → Arbiter → List.
  When the Arbiter sees data from multiple QDC blocks, it serves them in a round robin fashion, writing each data sample into the List block.

3. Parameter Settings

In the screenshots, some parameters are shown in the “Table 0”:

THRESHOLD (address 807): 2500
- Defines the trigger threshold.
DWELL (address 808): 100
- Defines how long (in clock cycles) the integration or readout time window stays active.
GAIN (address 809): 1000 (about 0.03 )
- A gain factor for the QDC or post-processing scaling.
ANALOG_OFFSET (address 0xFFFFFFF9): analog offset configuration

You set these values with the Set button, then confirm with Get to read back their current values.

4. Acquiring and Reading the Data

4.1 Resource Explorer in the GUI

After the design is running, the “List_0” block will collect data. Follow these steps to read it:

Open Resource Explorer
Select List_0 (or whichever list is storing your data).
Click Download or Start to transfer the data from the hardware FIFO into a binary file on your PC.
- You may see a dialog (like List_0 - 80B - Download) prompting you for the File Name, File Folder, Target Size, etc.
Once the file transfer completes, you have a raw .bin file (or .raw), typically in the folder you specified (e.g., c:\temp\arb1.raw).

4.2 Decoding with HxD

Open HxD (or any hex editor).
Load the downloaded binary file (e.g., arb1.raw).
You will see lines of hexadecimal bytes plus an ASCII “decoded text” on the right.
Each data record (a few bytes or words) corresponds to a sample from one of the channels.
Typically, the last byte MSB in each data record includes the channel ID (i.e., which channel triggered).

In many designs, the data format is [DATA0, DATA1, ... CHANNEL]. By examining the hex dump, you can see how each sample is structured:

For instance, if each record is 8 bytes, the final byte might be the channel number (0, 1, 2, etc.).
The rest contains the measured amplitude, integral, or timestamp bits.

Use your knowledge of the firmware to parse out the fields properly. For example:

XXXXXXXX: QDC..|...TIMESTAMP..|CH

00002630: 39 02 C5 E3 9F F8 05 00 (…)

00002638: D7 01 A7 E1 9F F8 05 00 (…)

5. Help on the Round Robin FIFO Arbiter

Below is a concise summary of how the Round Robin FIFO block operates:

IN (N bits): Data input. Multiple such inputs (e.g., 4 or more) can be handled.
DV: “Data Valid” input. High when that channel has active data to send.
BUSY (input): If high, it disables new data processing (a global “pause”).
CLK: System clock (e.g., 50 MHz or 80 MHz).
RESET: Forces the arbiter to clear its queue and start from the first channel.

Outputs

BUSY (per channel): Notifies an upstream block that this particular channel is currently being serviced.
DATA: The selected channel’s data.
ADDRESS: Identifies which channel (or memory address) is being serviced.
A+D: A combined bus that includes both address and data in one output word.
DV: High when valid data appears on DATA.

The block rotates through each channel in a fair manner. If a channel is inactive (DV = 0), it is skipped immediately. Once the last channel is reached, the arbiter loops back to the first.

This fairness strategy avoids data-loss due to a single channel flooding the bus.

6. Conclusion

By combining triggers, baseline restoration, and QDC measurement blocks, and then funneling multiple channels into a single Round Robin Arbiter, we achieve an efficient multichannel readout. The final results get stored in the List block for easy retrieval.