Lab 20 - Multichannel Design using Sub-Designs

In this lab, we extend the Lab 19 single-channel readout design into a multichannel setup by creating a sub-design that can be instantiated multiple times in the top-level schematic. This approach greatly simplifies maintenance and reuse of repeated channel logic.

1. Overview

  1. We create a sub-design called core_block that implements the processing chain for a single channel (trigger, baseline restore, QDC, etc.).
  2. The top-level design then instantiates this core_block sub-design multiple times—one for each ADC channel.
  3. We will route the outputs (DATAPACK, DV, etc.) from each channel into a Round Robin Arbiter (as in Lab 19), which in turn feeds a List block for data storage.
  4. Additional signals (like MONITOR) are fed into an Oscilloscope block for real-time visualization.

By turning the single-channel logic into a sub-design, we only build and maintain the logic once. Then, in the top-level design, we simply specify how many copies (channels) we need.

2. Creating the core_block Sub-Design

2.1 New Sub-Design

  1. From the main project, click the “plus” button (+) to create a new page/sub-design.
  2. Rename it to core_block.

Example Sub-Design Icon

Creating a new sub-design
Creating a new sub-design

2.2 Replicate the Single-Channel Logic

Inside core_block:

  • Import or recreate the single-channel chain from Lab 19. That typically includes:
    • A Trigger LE Hyst block (or similar trigger).
    • A Baseline Restorer block.
    • A QDC (Charge-to-Digital Converter) block.
    • Any needed constants or registers.

In Lab 19, these were directly in the main design. Now we move them into the sub-design.

Single-Channel Logic Example

Single-channel schematic excerpt
Single-channel schematic excerpt

3. Making the Sub-Design Ports

We replace the direct connections (e.g., from an Analog Pin) with ports that allow signals to be passed in and out of core_block.

3.1 Input Ports

  • DATA_IN (Array Port)
    16-bit wide. Each channel in the top-level will have its own analog input.
  • THRESHOLD (Common Port)
    16-bit wide. A single threshold value applies to all channels (if desired).
  • INT_SAMPLES (Common Port)
    16-bit wide. Integration length for the QDC.
  • GAIN (Common Port)
    16-bit wide. Gain factor.
  • ANALOG_OFFSET (Common Port)
    16-bit wide. Offset or pedestal correction.

Defining Ports

When creating each port, you can specify:

  • Number of Bits: e.g., 16 for the analog data, threshold, gain, etc.
  • Multichannel Behaviour: Choose ARRAY for signals that differ for each channel, or COMMON for signals that are shared across all channels.

Port Definition Dialog
Port Definition Dialog

3.2 Output Ports

From the single-channel chain, we make the following outputs:

  • DATAPACK (Array or single wide bus)
    Typically 56 bits, combining integrated result, optional timestamp, channel ID, etc.
  • DV (Data Valid)
    A 1-bit signal indicating valid data is present in DATAPACK.
  • MONITOR (Analog or processed signal)
    This is the input signal minus the baseline, often used for debug or display.
  • INT_MON (Integration Monitor)
    A digital 1-bit signal that goes high during QDC integration.
  • TRIGGER (Trigger Active)
    A digital 1-bit signal that goes high when the trigger is active.

Sub-Design Schematic Entries

Schematic entry blocks for input/output signals
Schematic entry blocks for input/output signals

4. Top-Level Design

After saving the core_block design, double-click on the top page (or “Top”).

4.1 Placing the Sub-Design

  1. From the Toolbox, select Sub-design → Multichannel Sub-Design.
  2. Insert the core_block sub-design into your main schematic.
  3. In the properties dialog, choose the number of channels. For example, 2.

A single “composite block” now appears in the main schematic, representing two identical channels. Each channel has its own DATA_IN port, while THRESHOLD, GAIN, etc. are shared.

Example: Two-Channel Sub-Design

Custom block with 2 channels
Custom block with 2 channels

4.2 Connecting Signals

Block diagram
Block diagram

  • Analog Input
    • If you have two ADC channels (A0, A1), connect each to the DATA_IN[0..1] ports of the sub-design.
  • Threshold, Dwell, Gain
    • These are common parameters, so you only have one line or register for each, connected to the sub-design’s common port.
  • DATAPACK / DV
    • From the sub-design, each channel’s DATAPACK and DV lines go into a Round Robin Arbiter to handle multichannel data readout.
  • Arbiter
    • The arbiter outputs a single DATA line and a DV line that get stored into a List block.
  • List block
    • Collects data from the arbiter in FIFO fashion. This is the same concept as Lab 19.
  • Oscilloscope
    • Connect any signals of interest (e.g., MONITOR, TRIGGER, INT_MON) to scope channels so you can visualize them live.

Top-Level Schematic Example

Top-level schematic with two sub-design channels
Top-level schematic with two sub-design channels

By replicating channels in the sub-design, you avoid copying/pasting the same logic for each channel. Instead, the sub-design is parameterized with ARRAY ports for per-channel signals and COMMON ports for shared configuration parameters.

5. Testing the Multichannel Design

  1. Generate or Synthesize your firmware project.
  2. Program the device with your new design.
  3. Configure the threshold, dwell, gain, etc., in the Resource Explorer table (or via register writes).
  4. Provide test signals to each ADC channel (A0, A1, etc.).
  5. Observe the waveforms on the Oscilloscope (monitoring MONITOR, TRIGGER, INT_MON, etc.).
  6. Trigger the readout: data from both channels should appear in the List memory after passing through the Round Robin Arbiter.

At this point, you have a multichannel design that is functionally equivalent to the previous Lab 19 design but uses sub-design principles for clean, scalable architecture.

6. Readout data

Repeat the steps from Lab 19 to read out the data from the List block. You can use the same Resource Explorer and HxD tools to download and decode the data.

7. Conclusion

  • We created a core_block sub-design that encapsulates one channel’s trigger, baseline restoration, and QDC functions.
  • We instantiated multiple copies of this sub-design in the top-level schematic, using ARRAY ports for per-channel inputs and COMMON ports for shared configuration.
  • We used a Round Robin Arbiter to combine data from multiple channels into a single output stream.
  • The approach is cleaner and more maintainable than manually duplicating each channel’s blocks.

This concludes Lab 20 on Multichannel Design using sub-design blocks. You can extend this technique to any number of channels, each referencing the same core logic.

Repository

You will find the full project in the Gitlab repository.