Lab 21 - Sub-Block Instances

In Lab 20, we created a single sub-design (core_block) and used the Multichannel Sub Design feature to automatically replicate that block for multiple channels (i.e., “array ports”). In Lab 21, we achieve an equivalent multichannel result, but without using the built-in “multi-channel” feature. Instead, we copy (instantiate) the sub-design manually multiple times in the top schematic.

1. Overview

1. Sub-Design creation: We build a single-channel processing chain (trigger, baseline restore, QDC, etc.) as a sub-design.
2. Manual Replication: Instead of using an “array port,” we simply place two (or more) copies of the same sub-design on the top-level schematic. Each sub-block is an identical instance of the single-channel core.
3. Top-Level Connections: We connect each instance to its own analog input, parameters, and output lines (DATAPACK, DV, etc.). These outputs then feed a Round Robin Arbiter and List block, just like before.

The main difference from Lab 20 is that here each sub-design instance is an independent block, so we do not rely on the “ARRAY” concept. We can rename or re-wire each instance as we wish.

2. Creating the Sub-Design

2.1 Add a New Sub-Design

1. Open your project’s block hierarchy panel (often shown on the left).
2. Click Add new subdesign (the “+” button).
3. Name it, for example, my_core_block.

Right click on the sub-design and rename it

A new blank schematic page (sub-design) opens.

2.2 Single-Channel Logic & Ports

Inside my_core_block, place your single-channel chain:

• Trigger block (e.g., Trigger LE Hyst)
• Baseline Restorer
• QDC
• Merger: to combine the QDC output and timestamp into a single data packet (DATAPACK).

Then, create ports (in/out terminals) for signals such as:

• DATA_IN (16 bits)
• THRESHOLD (16 bits)
• GAIN (16 bits)
• INT_SAMPLES (16 bits)
• DATAPACK (e.g., 56 bits, the consolidated data output)
• DV (data valid signal)
• MONITOR, INT_MON, TRIGGER (monitoring / debug signals)

Tip: Right-click on a pin in your schematic, select Pin Menu → Fanout pin to port to quickly create a port from that connection. Then name it appropriately.

Since we do not use the multichannel/array approach here, each port is effectively a single port per instance. (No array settings needed.)

3. Instantiating Multiple Copies

3.1 Return to Top-Level Schematic

1. Save the sub-design.
2. Go back to the top schematic (or “main” page).

3.2 Place Each Sub-Design

1. From the Toolbox (right-click in the schematic), choose
   Sub-design → Select Sub-design
   and pick my_core_block.

2. Click on the schematic to place the sub-design instance. This gives you one block representing your single-channel logic.
3. Repeat step 2 to place a second instance of the same sub-design. Now you have two copies of the same logic.

3.3 Wiring the Instances

Since each sub-block is independent, you must manually connect each block’s ports:

• DATA_IN: For instance 0, connect to Analog Input A0. For instance 1, connect to Analog Input A1.
• THRESHOLD, GAIN, INT_SAMPLES: If these are shared values, you can connect the same register output or constant block to both sub-blocks. If each channel needs a different threshold, give each block its own register or constant.
• DATAPACK & DV: Each instance outputs these. Combine them (2 lines each) into a Round Robin Arbiter (IN0 / DV0, IN1 / DV1).
• MONITOR, INT_MON, TRIGGER: Wire these signals to an Oscilloscope or other debug blocks as needed.

3.4 Common Post-Processing

Once data is combined by the Round Robin Arbiter, it typically goes into a List block (FIFO) for readout—same as in Lab 19/20. In the example diagram:

• Each sub-block’s DATAPACK → Arbiter input
• Each sub-block’s DV → Arbiter “Data Valid” input

The Arbiter merges them into a single data stream, stored in the List block.

4. Advantages & Considerations

• Pros:
  • Straightforward: each sub-design instance is fully independent.
  • Easy to customize each channel’s parameters or wiring.
• Cons:
  • Extra manual steps if many channels. (By contrast, the “multichannel sub-design” with array ports automates replication.)
• No Array Ports: Because each instance is a separate block, there is no array concept. All ports are single signals for that one channel.

5. Testing

1. Compile/Synthesize the design.
2. Program your hardware.
3. Configure the threshold, gain, etc. for each sub-block if needed (via registers).
4. Inject signals into the two analog inputs (A0, A1).
5. Observe on the oscilloscope if triggers are generated, if the QDC integrates properly, and check that data is stored in the List block after passing through the arbiter.

6. Conclusion

This lab demonstrates how to instantiate multiple identical sub-design blocks manually, instead of using the built-in multichannel array feature. Each sub-block implements the same channel logic. You then wire them individually at the top level for as many channels as you need.

• Lab 19 replicate the same logic for multiple channels using a Round Robin Arbiter and List block.
• Lab 20 used a single sub-design with array ports.
• Lab 21 replicates the sub-design multiple times, no array ports required.