In this lab, we start from Lab 20 (the single-channel design) and create a sub-design that implements the logic for a single channel. We then instantiate it multiple times in the top-level design using multiple sub-design instances.
However, we also move the registers and oscilloscopes inside the sub-design itself, rather than keeping them in the top design. This approach yields a cleaner top-level schematic and gives each sub-design instance its own independent register file and oscilloscope.
1. Sub-Design Setup
1.1 Sub-Design with Registers and Oscilloscope
Within the sub-design (let’s call it core_block), we include:
- Logic for a single channel (trigger, baseline restoration, QDC, etc.).
- Registers for configuration (e.g.,
THRESHOLD,GAIN,INT_SAMPLES). - Oscilloscope for monitoring signals.
Unlike previous labs, we place all these registers and the oscilloscope inside the sub-design.
1.2 Address Assignment for the Sub-Design
While the sub-design is open, we assign addresses for:
- Registers (e.g., THRESHOLD, GAIN, INT_SAMPLES).
- Oscilloscope (for data capture).
Because they are inside a sub-design, these addresses are relative to the sub-design’s base address. When we have multiple instances of the same sub-design, each instance will have its own base address, which is added to these relative offsets.
By clicking Auto Assign, the tool automatically sets addresses for the registers and oscilloscope, and it allocates address space for the sub-design according to the total size of its internal components.
2. Top-Level Integration
2.1 Placing the Sub-Design and Defining Base Addresses
In the top design, we place our core_block sub-design multiple times to create multiple channels. Each instance has:
- A unique name (Designator) to avoid name conflicts.
- A base address that determines where its internal registers and oscilloscope appear in the global address map.
Make sure each instance has a different name (e.g., core_block_1 vs. core_block_2) and a different base address if you want separate memory maps.
After placing multiple instances, each channel (sub-design instance) has its own registers and its own oscilloscope, making the top design cleaner:
Here, we assign the base addresses to each core_block instance:
3. Testing the Design
3.1 Resource Explorer
Open the Resource Explorer and add the registers from the sub-design to the configuration table. Notice how each register’s name is prefixed with:
- The sub-design instance name.
- The channel or instance number.
Hence, if you have multiple core_block instances, you will see multiple copies of the same register name but with different addresses.
You can configure these registers independently, since each channel’s base address is different.
3.2 Independent Oscilloscopes
Each sub-design instance includes its own oscilloscope. Thus, you can open two separate scope windows and configure triggers separately for each channel:
For instance, set Trigger Channel 1 with a threshold of 2500 on the first sub-design’s oscilloscope, and do the same (or different) for the second sub-design’s oscilloscope. The integration time is different for each channel as you can see in D1
3.3 Single List Block
Despite having multiple channels, we still have one List block in the top design that collects the data. Each sub-design instance sends data to the Round Robin Arbiter, which then outputs to this single List block.
Alternating data (last byte) for each channel is shown in the List block dump on file:
4. Conclusion
By embedding registers and oscilloscopes within each sub-design instance:
- We achieve a cleaner top-level schematic (fewer blocks and wires on top).
- Each channel has independent parameter registers and independent oscilloscope capture capability.
- The sub-design’s memory addresses are mapped relative to each instance’s base address, allowing multiple channels without collisions.
This concludes Lab 22. You now have a multichannel design where each channel (sub-design instance) contains its own registers and oscilloscope, offering a modular and well-organized system.