Lab 24 - PID Controller

This lab explains the theory and implementation of a Proportional-Integral (PI) controller in FPGA, specifically for realizing an Automatic Gain Control (AGC) system. The AGC maintains a constant peak-to-peak amplitude of the input signal by adjusting the gain dynamically.

PID Controller Theory

A PID controller (Proportional-Integral-Derivative) is a feedback control loop mechanism widely used in industrial control systems. It continuously calculates an error value as the difference between a desired setpoint and a measured process variable, applying correction based on three terms:

• Proportional (P): Immediate response proportional to the current error.
• Integral (I): Response based on the accumulation of past errors, used to eliminate steady-state error.
• Derivative (D): Response based on the prediction of future errors from the rate of change.

In our design, we implement only the PI controller, thus eliminating the derivative term. The output of a PI controller is expressed mathematically as:

\[ u(t) = K_p e(t) + K_i \int e(t) dt \]

where:

• \( u(t) \): control output
• \( e(t) \): current error (setpoint - measured value)
• \( K_p \): proportional gain
• \( K_i \): integral gain

FPGA Implementation of the PID Controller

Input Signal Amplitude Extraction

This block calculates the amplitude of the incoming signal:

• The input analog signal is first processed by a Trigger LE Hyst block to detect valid signal events.
• A Baseline Restorer calculates and subtracts the baseline from the input signal.
• The corrected signal is then fed into a Peak Detector block, which captures the peak amplitude.
• The amplitude output (AMP) is obtained by subtracting the baseline from this peak.
• The Data Valid (DV) output indicates a valid amplitude measurement.

PID Algorithm Implementation

The following block diagram represents the PI controller logic:

• Error Calculation:

  • A DSP-SUB block calculates the error (Er) by subtracting the measured amplitude from the setpoint.

  Configuration of DSP-SUB block:

  

• Proportional Component (Sp):

  • Implemented using a FX GAIN block, multiplying the error by the proportional gain (Kp).

  Proportional gain configuration:

  

• Integral Component (Si):

  • An accumulator (DSP-ACCUMULATOR) integrates the error over time.
  • The accumulated integral is then multiplied by the integral gain (Ki) through another FX GAIN block.

  Integral accumulator configuration:

  

• Summation and Saturation:

  • The control output (Sg) is computed by summing the proportional and integral terms.
  • This output is then latched using a D LATCH RISING block.

  Summation block:

  

• Control Output Saturation:

  • The output is limited between 0x0000 and 0xFFFF to ensure it remains within a valid range.
  • The saturated value controls the input gain block.

  Saturation and Gain Block:

  

Oscilloscope Monitoring Block

To facilitate real-time monitoring and debugging, various signals are routed to an integrated oscilloscope block:

Monitored signals include:

• Input signal amplitude (Insig)
• Control output after saturation (outig)
• Proportional signal component (Speak)
• Error signal (Er)
• Proportional component (Sp)
• Integral component (Si)
• Combined control signal (Sg)
• Integral accumulator output (Sacc)

This block is invaluable for observing real-time behavior of the PI controller and making necessary adjustments to the gains.

Experimental Procedure

Open the resource explorer, configure the PID registers, and display the first four oscilloscope channels.

Adjust the detector emulator or signal generator to obtain a baseline near 0 (around 400) and an amplitude near 1500, with a repetition rate of 10 Hz:

Digitized input signal:

• Blue: Input signal
• Green: AGC output signal
• Cyan: Peak-baseline after AGC
• Magenta: Error signal

Step 1: Initial Parameter Setting

Set the PID parameters initially as follows:

Hex value 0xFF08 format represent a negative number in two complement

Perform a reset strobe. The oscilloscope displays:

• Blue: Input signal
• Green: AGC output signal
• Cyan: Peak-baseline after AGC
• Magenta: Error signal

Observe how the error signal starts large and gradually decreases to zero, stabilizing the output signal to match the setpoint (1000):

Step 2: Increasing the Setpoint

Change the setpoint to 1250. The error initially increases (negative), then settles back to zero, stabilizing the output signal amplitude at 1250:

Step 3: Decreasing the Setpoint

Change the setpoint to 100. The error initially increases (positive), then settles back to zero, stabilizing the output signal amplitude at 100:

Conclusion

This lab demonstrates a practical FPGA-based implementation of a PI controller designed for automatic gain control applications. By dynamically adjusting the gain based on measured signal amplitude, the PI controller maintains a consistent peak-to-peak amplitude, effectively compensating for variations in signal strength with ns delay response.