Lab 3 - Threshold Discriminator with Event Counter

This project demonstrates how to:

• Create and use custom registers in Sci-Compiler (e.g., THRESHOLD, RESET, COUNTS)
• Compare an analog input signal against a programmable threshold
• Count threshold‐crossing events
• View both analog and digital signals on the integrated Oscilloscope

In addition, we use a Pulse Generator as a test signal source, feeding the DT1260 input connector through a 5× attenuator.

1. Block Diagram

• Analog In Pin (A0): Receives the external signal (from the Pulse Generator output).
• GREATER Comparator: Compares A0 (>16-bit) to THRESHOLD register value.
• EDGE DET. RISE: Detects rising edges from the comparator output.
• COUNTER RISING: Increments on each rising edge (i.e., each time A0 crosses above threshold).
• REG: THRESHOLD: A 16-bit register to store the user‐programmable threshold value.
• REG: RESET: A register to reset the counter when toggled from software (write 1 then 0).
• REG: COUNTS: A 32-bit register holding the current count.
• Oscilloscope: Allows us to visualize the input signal (on Channel 1) and any digital lines (D0, D1, etc.).
• Pulse Generator (PWM): Generates a periodic pulse for testing; its output is routed externally into the A0 input.

2. Creating the Registers

1. Right‐Click on the pin or net you wish to turn into a register input or output.
   

   

2. Select “Fanout pin to Register.”

3. In the Configure Register dialog:

   • Mode: Bit Vector (for numeric registers).
   • Size: 16 bits (for THRESHOLD) or 32 bits (for COUNTS).
   • Register Name: e.g. THRESHOLD, RESET, COUNTS.

   

4. Press OK.

Repeat this for each register you need. You’ll see them appear in the schematic as mmcRegister blocks.

3. Assigning Register Addresses

After adding all registers:

1. Open Hardware → Resource Explorer → Memory Map.
2. Press Refresh then Auto Assign to allocate physical addresses.
   • For example:
     • THRESHOLD might get address 0x0
     • RESET might get 0x807
     • COUNTS might get 0x808

These addresses are how you read/write each register from software.

4. Connecting the Hardware

1. Output of the PWM (on DT1260 front panel, labeled I/O1 or similar) → through a 5× attenuator → CH1 input.
2. Ensure the analog input is set to 50 Ω termination if available.
3. This input is digitized and fed into the A0 pin of the FPGA design.

5. Using the Oscilloscope

1. Compile & Program your design to the DT1260.

2. In Resource Explorer, connect over USB (or Ethernet) and expand Oscilloscope → Oscilloscope_0.

3. Right-click → View

   

4. Channel Selection: Enable Channel 1 to see the incoming analog.

5. Trigger Mode: Auto or Single (to capture pulses).

6. Trigger Source: If you want the scope to trigger on the analog level, set Trigger Source = Channel 1 and Trigger Level (lsb) = e.g. 2200.

   • Important: This Oscilloscope trigger is not the same as the GREATER comparator threshold in your logic. They are independent settings.

6. Monitoring the Registers in a Table

1. In the Resource Explorer, under Registers, create a New Table.
   

   

2. Right click on Registers and then Add All to Table to populate the table with your discovered registers (THRESHOLD, RESET, COUNTS, etc.).

3. You can:

   • Write a value to THRESHOLD (e.g., 2200) and click Set.
   • Read the current COUNTS value repeatedly (click Get or Get All) to see how many times the analog signal has crossed the threshold.

4. Reset the counter by writing 1 to RESET and then 0 again.

Note: The threshold in the THRESHOLD register is for the logic comparator, NOT for the Oscilloscope’s trigger. Setting the Oscilloscope trigger level does not change the FPGA comparator threshold (and vice versa).

7. Observing the Signals

• Oscilloscope:
  • Channel 1 (analog trace): The actual input waveform.
  • Digital Lines (e.g., D0, D1) can be driven by the comparator or edge detector if you connect them. This allows you to see visually when the signal is above threshold or when the edge is detected.
• COUNTS register: Increments each time A0 surpasses the threshold (on a rising transition).

If you see the digital trace go high in the scope (above threshold) and the rising-edge pulse on another trace, you should also see COUNTS increment in the register table each time that pulse occurs.

8. Summary & Key Points

1. Threshold vs Oscilloscope Trigger: They’re separate parameters. The first is for your custom comparator logic, the second is for capturing the waveform in the scope.
2. Registers:
   • THRESHOLD (16 bits) sets the FPGA’s comparator threshold.
   • RESET is toggled (1 then 0) to clear the event counter.
   • COUNTS (32 bits) holds the number of threshold‐cross events.
3. Resource Explorer:
   • Oscilloscope tab to see waveforms.
   • Registers tab (New Table) to read/write your custom registers.
4. Hardware: Use a suitable attenuator and 50 Ω input to avoid saturating the analog input.

By combining the Comparator, Edge Detector, Counter, and memory‐mapped registers, you have a configurable threshold discriminator that counts how many times the incoming analog signal crosses the desired level.