Lab 7 - FPGA-Based Dwell Time for Precise Event Counting

In previous labs, the dwell time (the interval during which we count threshold crossings) was controlled by the PC simply by waiting a certain number of seconds in Python. That method, however, relies on software timing and the host operating system, which can introduce inaccuracies or jitter.

In Lab 7, we move the timing logic entirely onto the FPGA. We use the DT1260’s 65 MHz clock and a Timer (Start Stop) block to achieve a precise, hardware-controlled dwell period. The schematic below illustrates the new approach:

1. Schematic Overview

Design with hardware DWELL
Design with hardware DWELL

  1. REG: THRESHOLD

    • A 16-bit register controlling the comparator threshold (as before).

  2. Comparator (GREATER)

    • Compares A0 against THRESHOLD.
    • Output goes HIGH when A0 > THRESHOLD.

  3. EDGE DET. RISE (top, labeled U9)

    • Converts the comparator’s continuous signal into pulses on the rising edge.
    • This signal increments the Counter block, but only when the counter’s GATE is HIGH.

  4. REG: RESET

    • A 1-bit register for resetting the Edge Detector or other logic.

  5. Counter Rising

    • Counts the number of pulses from the comparator’s Edge Detector, while GATE = HIGH.

  6. Timer (Start Stop)

    • Receives a TARGET (the dwell time in clock cycles) from a 32-bit register called DWELL.
    • When we start the timer, it runs for exactly TARGET clock cycles (e.g., 65,000,000 cycles ≈ 1 second at 65 MHz).
    • At the end, it asserts EXPIRED = 1.
    • The timer’s RUNNING signal can be used to gate the counter, so the counter only increments during the dwell period.

  7. REG: DWELL

    • 32 bits wide. Holds the number of clock cycles for the dwell interval.
    • E.g., writing 65000000 sets a dwell time of ≈1 second.

  8. Edge Det. Rise (bottom, labeled U9 or U13 in the figure)

    • Another edge detector might convert the user’s write to RESET or a software command into a START pulse for the timer, etc.
    • The details vary based on how the schematic is wired, but the idea is that writing 1 to “start” the timer triggers it.

  9. REG: DATA_READY

    • Another 1-bit register that is set when the timer EXPIRED goes HIGH.
    • This tells software “the dwell period is finished” and that the COUNTS register is ready to be read.

  10. REG: COUNTS

    • 32 bits. Stores the final counter value after the dwell period ends.

Key Idea: By controlling the timer and using the EXPIRED output to latch DATA_READY, the FPGA precisely measures the counting interval using the 65 MHz clock. Software merely polls DATA_READY to know when the dwell period has ended and the COUNTS register is valid.

2. Operation Steps

  1. Write the desired dwell time to the DWELL register. (For 1 s at 65 MHz, DWELL = 65000000.)
  2. Start the timer (for instance, by toggling a register that drives the timer’s START input).
  3. The Counter is enabled (or “GATE” is high) during the timer’s RUNNING phase, so threshold-cross pulses are incremented.
  4. Once the timer hits DWELL cycles, it sets EXPIRED to 1 → sets DATA_READY to 1.
  5. Software polls or waits for DATA_READY = 1, then:
    • Reads COUNTS to get the final count.
    • Optionally writes DATA_READY = 0 or restarts the timer for another dwell period.

3. Python Script Example

Here’s a minimal Python script (lab7_hw_dwell.py) demonstrating how to use hardware-based dwell time:

from scisdk.scisdk import SciSDK
from scisdk.scisdk_defines import *
import time

# -------------------------
# 1) User-set parameters
# -------------------------
DWELL_VALUE = 65000000   # ~1 second at 65 MHz
THRESHOLD   = 2200       # Example threshold
REPEAT_MEAS = 3          # Number of dwell measurements to make

def main():
    # 2) Initialize SciSDK and connect to device
    sdk = SciSDK()
    res = sdk.AddNewDevice("usb:10500", "dt1260", "./library/RegisterFile.json", "board0")
    if res != 0:
        print("Error adding device:", sdk.s_error(res))
        return
    
    print("Connected to DT1260 with hardware-based dwell timer.")

    # 3) Configure registers
    # Set the threshold
    r = sdk.SetRegister("board0:/Registers/THRESHOLD", THRESHOLD)
    if r != 0:
        print("Error setting threshold:", sdk.s_error(r))
    
    # Set dwell time in clock cycles
    r = sdk.SetRegister("board0:/Registers/DWELL", DWELL_VALUE)
    if r != 0:
        print("Error setting dwell:", sdk.s_error(r))

    for i in range(REPEAT_MEAS):
        print(f"\nMeasurement {i+1} of {REPEAT_MEAS}")
        
        # 4) Start the timer

        r = sdk.SetRegister("board0:/Registers/RESET", 1)
        if r != 0:
            print("Error starting timer:", sdk.s_error(r))
        
        sdk.SetRegister("board0:/Registers/RESET", 0)

        # 5) Wait for "DATA_READY"
        while True:
            err, ready_val = sdk.GetRegister("board0:/Registers/DATA_READY")
            if err != 0:
                print("Error reading DATA_READY:", sdk.s_error(err))
                break
            
            if ready_val == 1:
                # Timer has expired
                break
            time.sleep(0.001)  # Poll every 1ms to avoid busy spinning

        # 6) Read the final counts
        err, counts_val = sdk.GetRegister("board0:/Registers/COUNTS")
        if err != 0:
            print("Error reading COUNTS:", sdk.s_error(err))
            counts_val = 0
        
        print(f"DWELL = {DWELL_VALUE} cycles, THRESHOLD = {THRESHOLD}, COUNTS = {counts_val}")

        # Clear DATA_READY if needed
        sdk.SetRegister("board0:/Registers/DATA_READY", 0)

    # 7) Cleanup
    sdk.DetachDevice("board0")
    print("\nAll measurements complete. Device detached.")

if __name__ == "__main__":
    main()

Code Explanation

  1. DWELL_VALUE = 65000000

    • We want exactly 1 second of counting at 65 MHz. If your clock is different, adjust accordingly.

  2. sdk.SetRegister(“board0:/Registers/DWELL”, DWELL_VALUE)

    • Programs the timer’s TARGET cycles.

  3. Starting the Timer

    • In this example, we assume writing 1 to a START_TIMER register triggers the Timer (the schematic might differ; rename as needed).
    • We then write 0 to ensure the timer sees a clean rising edge.

  4. Polling DATA_READY

    • The timer sets DATA_READY = 1 when it EXPIRED.
    • The script loops until DATA_READY == 1.
    • This ensures we wait for the dwell period to finish.

  5. Reading COUNTS

    • Once DATA_READY is 1, the COUNTS register holds the final count.
    • We read and log it.

  6. Repeat

    • We do multiple measurements (REPEAT_MEAS = 3) just to demonstrate a loop.

4. Key Takeaways

  1. Hardware Timing: Relying on the FPGA’s 65 MHz clock means precise, stable dwell intervals—no drift or OS scheduling delays.
  2. DATA_READY: Allows a simple handshaking mechanism—once the dwell interval expires, you know the final count is ready.
  3. Modular: The same approach can be extended to longer or shorter intervals, or to multi-channel counting applications.

With this design, your measurements will be much more accurate and repeatable than any software-based timing loop.

Repository

You will find the full project in the Gitlab repository.