Simulating an FPGA design before hardware implementation is crucial. It allows us to:

  • Verify functionality and logic without risking real hardware.
  • Test various input conditions (e.g., random pulses, high rates).
  • Identify bugs or timing issues early, saving time and resources.

In this lab, we create a simple block diagram with two triggers that detect pulses on separate channels. Each trigger output goes to a Gate & Delay block to generate a fixed‐length pulse. Then we take the coincidence of these two channels, and finally a monostable generates a constant‐width output pulse whenever both channels overlap in time.


Design of the Block Diagram

Below is the block diagram where:

  • Two Trigger LE blocks identify incoming pulses (one on A0, one on A1).
  • Each trigger output goes through a Gate & Delay block, producing a pulse of fixed width.
  • The two gated signals are fed into an AND gate to detect coincidence.
  • A Monostable (one‐shot) outputs a fixed‐length pulse when the AND is high.

Block Diagram
Block Diagram

[Figure: The two Trigger LE blocks feed Gate & Delay blocks, whose outputs go to an AND gate, then a Monostable. This final monostable generates a fixed‐length pulse in coincidence.]


Add Probes to the Simulation

We want to observe internal signals (e.g., triggers, gate outputs, AND result).

  1. From the Simulation menu, choose Insert Probe.
  2. Select the signals of interest and name each probe.
  3. Choose STD_LOGIC_VECTOR (or the appropriate data type) for each.

Insert Probes
Insert Probes

[Figure: In the Sci‐Compiler environment, selecting “Insert Probe” to add debug outputs for internal signals.]

Probe Configuration
Probe Configuration

[Figure: Naming the probe and choosing STD_LOGIC_VECTOR as the data type for the signal.]

Below, you see the block diagram with all the probes added:

Diagram with Probes
Diagram with Probes

[Figure: The same design, now showing multiple probes (the small tags) on relevant signals for simulation.]


Define the Simulation Input Stimulus

We need to replace each analog input (A0, A1) with a synthetic signal in the testbench. Sci‐Compiler provides several stimulus modes:

  • Constant: a fixed value signal.
  • File: a waveform read from a text file.
  • Signal Generator: a basic generator for exponential or rectangular pulses.
  • Detector Emulator: a more advanced generator with adjustable rate, amplitude distribution, noise, etc.

For this lab, we select the Detector Emulator with a 1 MHz rate and a Poisson distribution, so pulses arrive randomly:

Detector Emulator Setup
Detector Emulator Setup

[Figure: Configuring the “Detector Emulator” on input A0 with Poisson distribution, amplitude, and rate set to 1 MHz.]

We repeat the same steps for A1:

Second Channel Setup
Second Channel Setup

[Figure: The second analog channel (A1) also configured as a Poisson source at 1 MHz, ensuring random pulses on both channels.]

We can see from the preview plot that pulses are distributed randomly in time. This will produce events that sometimes coincide on A0 and A1, triggering our logic.

Note: If you try to simulate without defining a stimulus for all analog channels, you’ll get a simulation error:

Simulation Error
Simulation Error

[Figure: Example error when an analog channel has no defined stimulus, reminding you to configure all inputs.]


Run the Simulation

  1. Go to Simulation → Run Simulation.
  2. Set the simulation length in microseconds (e.g., 50 µs or 100 µs).
  3. Sci‐Compiler will launch Xilinx Vivado in the background to run the testbench.

Set Simulation Duration
Set Simulation Duration

[Figure: Choosing the run length of the simulation in microseconds.]

Vivado Launching
Vivado Launching

[Figure: Vivado is automatically invoked for the simulation process.]

When complete, you’ll see “Successfully compilation!”:

Compilation Success
Compilation Success

[Figure: Final success message from the simulation flow.]


Visualize the Simulation Results

To view waveforms:

  1. Simulation → View Waveforms Results opens GTKWave.
  2. A dialog appears with a list of testbench signals. Select the signals you want and press Insert.

GTKWave Setup
GTKWave Setup

[Figure: Opening GTKWave from Sci‐Compiler to examine the waveforms.]

Signal List
Signal List

[Figure: The top‐level testbench and internal signals. Highlight them, then “Insert” to add to the waveform viewer.]

Tip: Perform a Zoom Out to see the entire simulation:

Zoom Out
Zoom Out

[Figure: The minus‐magnifying‐glass button to zoom out and reveal the entire timescale of the run.]

Displaying Analog Inputs

  1. Right‐click A0 and A1 in the signal list.
  2. Data Format → Decimal.
  3. Data Format → Analog → Step for a stepped analog plot.
  4. You can also Insert Analog Height Extension to enlarge them vertically.

Analog Format Setup
Analog Format Setup

[Figure: Converting the signals to decimal, then to an analog style like “Step.”]

Analog Height Extension
Analog Height Extension

[Figure: Increasing the vertical space for each analog signal in GTKWave.]

With everything set, we see the analog pulses on A0 and A1, plus the digital signals from the triggers, gates, AND, and monostable:

Full Waveform View
Full Waveform View

[Figure: Final GTKWave display with both analog channels (blue or green lines) and digital signals (in separate rows).]

We can zoom in on any region of interest:

Coincidence Zoom
Coincidence Zoom

[Figure: A closer look shows pulses on both A0 and A1 overlapping in time, the AND signal going HIGH, and the monostable output generating a fixed‐length pulse.]

Notice that the monostable output is high only when the two gated signals (GD1 and GD2) are coincident, producing a stable output pulse with a fixed duration.


Conclusion

By simulating the design with random Poisson pulses on two channels, we verify that:

  • Each Trigger LE detects pulses above a threshold.
  • The Gate & Delay blocks generate fixed‐length pulses.
  • The AND gate checks for overlap between the two channels.
  • The Monostable produces a clean, fixed‐width output pulse upon coincidence.

This workflow—block diagram creation, adding probes, defining input stimuli, running the simulation, and visualizing with GTKWave—is a standard approach in Sci‐Compiler to ensure your logic behaves correctly before deploying to an FPGA.