Sim 4 - Design of a Baseline Restorer

In this lab, we implement and simulate a Baseline Restorer (BLR) module that locks on to the baseline of an incoming signal while inhibiting baseline updates whenever a pulse is detected. Below is an overview of the BLR concept, the block diagram, and the simulation results to verify the design.

1. Introduction: What is a Baseline Restorer and Why Use It?

Many detector systems (e.g., charge‐sensitive preamplifiers) produce pulses on top of a baseline or offset. Typical issues include:

• Baseline drift due to slow variations,
• DC offset or low‐frequency noise shifting the baseline.

A Baseline Restorer (BLR) keeps the baseline near zero (or some reference level) by removing slow drifts and offsets. However, it must suspend its baseline estimate whenever a real signal pulse arrives to avoid corrupting the baseline with the pulse peak.

Advantages:

• A stable baseline improves the signal‐to‐noise ratio (SNR).
• It prevents long‐term offset changes from degrading the pulse amplitude measurement.

2. Block Diagram

Below is the schematic in Sci‐Compiler:

Key components:

1. Trigger LE Hyst (U5)

   • Detects rising edges above a certain threshold.
   • Outputs a TRIGGER signal to indicate a pulse arrival.

2. Delay (U6)

   • Delays the TRIGGER by 25 samples (a “pre‐trigger”).
   • Used to position the baseline inhibition window correctly around the pulse.

3. Timer (Start‐Stop) (U17)

   • On receiving START from the TRIGGER, counts 1000 samples.
   • While the timer is RUNNING, the BLR is inhibited (no baseline update).

4. Logic Not (U7) and AND (U8)

   • Generate the BLR enable line by inverting the timer output.
   • If timer is running → BLR is disabled.
   • Once the timer expires → BLR re‐enabled.

5. Delay Line (U11) and Subtractor (U2)

   • The delay line shifts the incoming samples by 128 cycles.
   • The subtractor calculates the difference: A0(n) − A0(n − 128), estimating the drift or offset.

6. Accumulator (U1) + Shift (U19)

   • Integrates the difference from U2.
   • Shifting right by 7 bits (»7) divides by 128, effectively performing a moving average.

7. ProbeBL

   • The final computed baseline, displayed for simulation. In a real system, you might use this signal to correct the incoming data by subtracting the baseline offset.

3. Logical Operation

1. Pulse Detection

   • When A0 exceeds the configured threshold in Trigger LE Hyst, the TRIGGER output goes HIGH.

2. Baseline Inhibition

   • The TRIGGER starts the Timer.
   • For 1000 samples, the timer is RUNNING and the BLR is disabled (CE=0).
   • During this time, the BLR does not update the baseline, preventing pulse peaks from affecting the baseline estimate.

3. Return to Updating

   • After the timer expires, the logic sets CE=1 again → the BLR resumes integrating the baseline.

4. Delay Lines

   • U6 (25‐sample delay) acts as a pre‐trigger offset, often used to align the gating with the actual signal.
   • U11 (128‐sample delay) helps form a moving average window. Subtractor U2 produces A0(n) − A0(n − 128), which is accumulated in U1 and then shifted to get an average.

4. Simulation Results

4.1 Baseline Correctly Maintained

• A0[15:0]: The raw input pulses (exponential shape).
• ProbeEN: The BLR enable (CE). 0 = baseline updates inhibited, 1 = baseline updates active.
• ProbeTRG: The trigger bit, goes HIGH when a pulse is detected.
• ProbeDIFF: Output of U2, showing the difference (close to zero when baseline is stable).
• ProbePRETRG: The pre‐trigger (delayed trigger) output from U6.
• ProbeBL: The calculated baseline from the accumulator and shift. It stabilizes around a certain value, and remains flat (unchanged) during pulses due to the BLR inhibition.

We can see that around 40 µs, a large pulse arrives; the baseline stops updating (goes flat). After ~50 µs (once the timer finishes), the BLR resumes adjusting the baseline slowly.

4.2 Enable Always HIGH

If we disable the inhibition logic and force ProbeEN = 1 always, the BLR integrates even when a pulse is present. This causes:

• ProbeBL to jump sharply whenever a pulse arrives.
• Potentially large baseline errors.

5. Tutorial / Instructions

1. Blocks

   • Trigger LE Hyst to detect the pulse.
   • Timer to define the 1000‐sample “inhibition window.”
   • Delays for pre‐trigger offset (U6=25) and baseline averaging (U11=128).
   • Subtractor + Accumulator + Shift to form the moving average.
   • Logic to produce the CE (Enable) signal for the BLR.

2. Parameter Values

   • Threshold in Trigger LE Hyst: 500 (ADC counts).
   • Delta: 1 to avoid toggling around threshold.
   • Timer: TARGET = 1000, PERIODIC=off.
   • Delay U6=25, U11=128.
   • Shift=7 bits → divide by 128.

3. Simulation Setup

   • Detector Emulator on A0: configure an exponential pulse with amplitude ~2000, tau, etc.
   • Run simulation and open GTKWave.
   • Observe the BLR enabling/disabling in sync with pulses.

4. Data Interpretation

   • The baseline remains stable except during pulses, when the logic “freezes” updates.
   • This ensures pulses don’t corrupt the baseline estimate.

6. Conclusion

Our Baseline Restorer design uses a Trigger to detect pulses and a Timer to hold off baseline updates for a fixed interval (1000 samples). Afterward, the module resumes integrating the drift in the input signal. This ensures a robust baseline estimate free from transient distortions caused by large pulses, which is crucial in nuclear spectroscopy and other signal processing scenarios where accurate amplitude measurement is required.