Sim 7 - Simulating a Simple State Machine for Gamma Ray Burst Detection

In this lab, we simulate a simple application where a gamma-ray detector must recognize a high-rate (“burst”) event. We measure the event rate in a defined time window (e.g., 100 µs). If the rate exceeds a certain threshold, the detector begins counting gamma events for a specified integration window. The total number of events in that window is then stored in a FIFO list.

1. Gamma Ray Burst Detection

1.1 Overview of the Block Diagram

Below is the top-level schematic. We use several functional blocks to implement rate measurement, threshold comparison, a timer, and a simple state machine logic to handle acquisition and data storage.

1. Analog Input Pin (A0)
   The input signal representing gamma events arrives here. Each event is a digital pulse or transition used to measure the rate.

2. Trigger LE Hyst (U1)

   • Generates a trigger (P_trig in the SIM block U11) whenever the input crosses a specific threshold (set by the block’s THRESHOLD input).
   • Outputs a TRIGGER signal for each detected event.

3. Freq Meter (U2)

   • Measures how many triggers occur within a specific interval (e.g., 6500 clock cycles ~ 100 µs).
   • The measured frequency is output to P_freq (visualized by SIM block U10).

4. Comparator (GREATER, U13)

   • Compares the measured frequency (P_freq) with a threshold (e.g., 50).
   • If P_freq > 50, the output is high, indicating a potential “burst.”

5. FF SET-RESET (U14)

   • Acts like a simple latch for the state machine.
   • When GREATER goes high, SET is triggered → Acquisition State (e.g., P_sm_acqon high).
   • When the Timer block signals an expiry, RESET is triggered → returns to Rate Measurement State.

6. Timer (Enable, U15)

   • Once the system enters the Acquisition State, the timer starts counting up to a specified integration time (TARGET = 10 000 cycles, for instance).
   • While ENABLE is high, the timer runs. When it reaches TARGET, it sets EXPIRED high for one clock cycle.

7. Counter Rising / D Latch (U4, U20)

   • Counts the gamma events while in the Acquisition State.
   • The D Latch can capture or hold the count value before writing it to the FIFO.

8. List (U5)

   • A FIFO where final counts are stored. When the timer expires, the count is latched and written to the list.
   • This allows offline analysis of how many events occurred in the burst window.

9. SIM blocks (U8, U9, U10, U11)

   • Used for simulation output signals like P_freq, P_trig, P_sm_acqon, P_sm_send.

Overall Flow:

1. Rate Measurement
   • The Freq Meter measures triggers in a time window.
   • If P_freq < threshold, the system remains in Rate Measurement State.
2. Threshold Exceeded
   • If P_freq > threshold, the FF Set output (P_sm_acqon) goes high → Acquisition State.
   • The Timer (U15) starts; the counter begins accumulating gamma events.
3. Timer Expiry
   • When the Timer reaches the integration window, it sets EXPIRED high.
   • The count is written to the List. The FF is reset → system returns to Rate Measurement State.

2. State Machine Description

We can think of this design as having two main states:

1. Rate Measurement State
   • Monitor event rate within a fixed time window (e.g., 100 µs).
   • Use the Freq Meter to generate P_freq.
   • Comparator checks if P_freq exceeds the threshold (50 in this example).
2. Accumulation State
   • Once P_freq is above 50, P_sm_acqon is set to 1 by the FF block.
   • The Timer starts, and the Rising Edge Counter accumulates gamma triggers.
   • When EXPIRED is asserted, the final count is written to the FIFO List, and the system returns to Rate Measurement State (the FF is reset).

The “state” is effectively held in a flip-flop register (FF SET-RESET block). The comparator transitions the state machine from Rate Measurement to Accumulation. The Timer’s expiry transitions it back.

3. Simulation Results

3.1 High-Rate Burst

When simulating a high-rate signal arriving at A0:

• As soon as the measured frequency P_freq surpasses 50, P_sm_acqon goes high, and the Timer starts.
• The Counter accumulates incoming events during this Acquisition State.
• Once the Timer hits its expiration, P_EXPIRED goes high for one clock cycle, the count is written to the FIFO, and the state machine reverts to Rate Measurement.

3.2 Zoomed View: Rate to Accumulation Transition

• At the transition point, the comparator’s output sets P_sm_acqon = 1.
• The Timer’s countdown begins, the event counter is active.
• After the window, the FIFO write occurs, and the system resets P_sm_acqon.

3.3 Writing Data into the FIFO

• Here we see the exact moment the latched count is transferred to the List (FIFO).
• This logic ensures each burst count is captured in one location for later readout.

4. Conclusion

This simple state machine handles gamma burst detection by:

• Continuously measuring input rate in a short time window (via Freq Meter).
• If the measured rate crosses a threshold, it switches to an accumulation mode, counting all events in a specified integration window (managed by the Timer).
• At the end of that window, the accumulated count is written to a List FIFO, and the state machine resets to measure the rate again.

Through simulation, we verify correct transitions, data capturing, and the final FIFO write, confirming the design is functional for gamma burst detection tasks.