Sci-Compiler

Application-Notes List, Time Tag, Sci-SDK, Readout List Time Tag Basic Example Dt1260 Sci-Sdk Readout An010

Time-tag events and readout data using List Component

Introduction Time tagging of events in a high-energy detector system refers to the process of accurately measuring and recording the timing information associated with the detected events.

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Application-Notes List Scaler Basic Example Dt1260 Sci-Sdk

Scaler with programmable d-well time

Introduction This application note explain how to design a firmware that can work with all Sci-Compiler FPGA compatible models that allows to use the board as a Multievent latching scaler housing up to both analog and digital channels.

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Hands-On Hands-On, List, Timestamp, Trigger, Packet Dt1260 List Timestamp Trigger Packet

Lab 10 - Timestamp and Time‐over‐Threshold with List Data Buffer

This example measures both Time over Threshold (ToT) for an analog signal and a Timestamp associated with each event. The design then stores (or “lists”) these measurements in a memory buffer for later readout.

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Hands-On Hands-On, Sci-Sdk, List, Timestamp, Trigger, Packet, ToT, ToF Dt1260 Sci-Sdk List Timestamp Trigger Packet ToT ToF

Lab 11 - Python Readout, Decoding, and Plotting of ToF and ToT

In this lab, we build on Timestamp and Time‐over‐Threshold with List Data Buffer (Lab 10), where data from each event contains both ToT (Time‐over‐Threshold) and ToF (Time‐of‐Flight) values.

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Hands-On Hands-On, Dt1260, Readout, Arbiter, List Dt1260 Readout Arbiter List

Lab 19 - Multichannel Readout Using the Round Robin Arbiter

In this lab, we demonstrate how to acquire and read out data from multiple input channels in a Round Robin fashion using a FIFO-based arbiter.

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Hands-On Hands-On, Dt1260, Multichannel, Sub-Design, Readout, Arbiter, List Dt1260 Multichannel Readout Sub-Design Arbiter List

Lab 20 - Multichannel Design using Sub-Designs

In this lab, we extend the Lab 19 single-channel readout design into a multichannel setup by creating a sub-design that can be instantiated multiple times in the top-level schematic.

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Hands-On Hands-On, Dt1260, Multichannel, Sub-Design, Readout, Arbiter, List Dt1260 Multichannel Readout Sub-Design Arbiter List

Lab 21 - Sub-Block Instances

In Lab 20, we created a single sub-design (core_block) and used the Multichannel Sub Design feature to automatically replicate that block for multiple channels (i.

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Hands-On Hands-On, Dt1260, Multichannel, Sub-Design, Readout, Arbiter, List Dt1260 Multichannel Readout Sub-Design Arbiter List

Lab 22 - Memory-Mapped Components in a Sub-Design

In this lab, we start from Lab 20 (the single-channel design) and create a sub-design that implements the logic for a single channel.

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Tag: List