Logo Logo
Logo ×
  • Home
  • My Sci-Compiler
  • Gitlab
  • Community forum
Site Logo
  • FAQs
  • Features
  • Resources
    • Application Notes
    • Videotutorial
    • User Guide
    • Case Studies
    • Hands-on labs
    • Sci-SDK
  • Download
Login
user image
  • Home Page
  • Tags
  • Logic

Tag: Logic

Hands-On Hands-On, Simulation, Gate Delay, Trigger, Monostable, Logic Simulation Gate Delay Trigger Monostable Logic

Sim 1 - Introduction to Simulation

Simulating an FPGA design before hardware implementation is crucial. It allows us to: Verify functionality and logic without risking real hardware.

Read More +

IEEE NSS MIC RTSD 2023 Conference.

Meet us in Vancouver from 6 to 10 of November 2023, @ the IEEE Nuclear Science Symposium, Medical Imaging Conference and Room Temperature Semiconductor Detectors 2023


Introducing Sci-Compiler Lucca Edition

We are pleased to announce the release of Sci-Compiler Lucca Edition. This new version brings powerful features.


Sci-Compiler 2023.7.25.3 introduces integrated documentation

Create and associate project documentation, either at the design or sub-design level, using a user-friendly editor


Featured Articles

  • Position Sensitive Scintillation Detector
  • Custom Packet Data Decode
  • What is Sci-Compiler

FAQs

Application Notes

Features

News

Case Studies

Hands-on labs

User Guide

  • Introduction to Sci-Compiler
  • Installation
  • My Sci-Compiler
  • Getting Started
  • Design with Sci-Compiler
  • Sci-Compiler Components
  • Sci-SDK
  • Read-out Data with Sci-Compiler

Supported Hardware

Sci-Compiler
  • Latest version: 2025.3.20.1
  • Request a quote Sci-Compiler
    Sci-Compiler Smart kit
  • Remote API status
Support
  • Getting Started
  • Supported Hardware
  • News
  • Application Notes
  • Videotutorial
  • Contact Us
  • EULA
Designed by Nuclear Instruments Srl
for CAEN SpA instrumentation.
Nuclear Instruments srl logo
CAEN SpA logo

Sci-Compiler © 2025. All Rights Reserved