When the user has finished to place the blocks on the diagram and to connect them, he can compile its graphically designed FPGA firmware. Before starting the compilation, the user has also to properly set the path of the Vivado and/or Quartus executable files in the “Settings” window, as described in the Sci-Compiler Configuration section.
The firmware compilation on the user computer starts by pressing the “Compile” button in the “Compiler” group of the “Home” toolbar. The button is immediately transformed in the “Stop Compilation” button in order to stop the compilation process if needed. Automatically, the “Compiler Output” section is displayed in order to show the messages describing the processes that are occurring. At the same time, the status label on the left corner of the status bar changes from “IDLE” to “COMPILING” and the progress bar on the right corner of the status bar starts to being updated to show the progression of the compilation process.
The first compilation step is executed by the SCI-Compiler and consists in the generation of the VHDL code from the user designed diagram. The various operations are described and reported in the “Compiler Output” in blue, while eventual errors will be displayed in red. In particular, the registers and the signals map are generated and mapped on the correct addresses. Then, to each block used in the diagram is assigned a name (“U” + incremental number) and the correspondent HDL code is generated in the “HDL/pcores” folder of the current project. At this point, the HDL code can be assembled for all the file used in the “Project File”, i.e. the top page or the main diagram and all the sud-design diagrams, and the correspondent .vhd files are generated in the “HDL” folder of the current project.
The second compilation step involves the creation by the SCI-Compiler of a C library and of an example project (that could be compiled in VC++, gcc, XCODE) in the “library” folder of the current project that can be exploited by the user to test the board communication. In addition, a .json file is created in the same folder: it contains all the defined registers, oscilloscopes, list modules and logic analyzers blocks in order to transmit all the necessary information to the Resource Explorer tool, which allows to test the functionalities of the designed firmware.
In the third compilation step the SCI-Compiler generates a .tcl file in the “HDL” folder of the current project that is used to execute from the shell the Vivado or Quartus program, depending on the target board chosen for the project. In fact, Vivado and Quartus are, respectively, the Xilinx and the Altera software allowing the FPGA firmware compilation and bitstream generation. For this reason, the SCI-Complier requires the Vivado software or the Quartus software in order to compile a firmware for the DT5550 or for the V2495, respectively. The output of the compiler software execution is redirected to the “Compilation Output” and visualized in black, with the warning massages displayed in orange and the error messages reported in red. The firmware compilation is composed by various phases: the analysis and synthesis of all the components, their mapping, their placing and routing, where the optimization of the space and time constraints is taken into account.
The final compilation step is represented by the generation of the bitstream file that is required to program the FPGA, a configuration file compatible with the supported platform: in the case of the DT5550 it is a.bit file, while in the case of the V2495 it is a .rpd file. All the output files are generated in the “output” folder of the current project.
In case of errors that occurs during the firmware compilation, the process is stopped, the “Stop Compilation” button is transformed again in the “Compilation” button to start a new compilation, the progress bar is reset and the status bar returns in the “IDLE” state. The user can then use the error messages to solve the issues and start a new compilation. If no errors occur, the compilation process continues till the end and the SCI-Compiler sends the message “Successful compilation!”. Also in this case the progress bar is brought back to the start, the status bar returns in the “IDLE” state and the “Stop Compilation” button changes to “Compile” button to allow a new firmware compilation process.
The button “Compile SDK” generate the SDK library and examples (library folder in the project folder tab) without recompiling the entire project and without generating bitstream.