Once the firmware compilation process is terminated successfully and the bitstream file has been generated, the user can program the DT5550 or the V2495 FPGA, depending on the board selected for the project. The boards have to be powered and connected to the computer, as described respectively in the board user manuals.
The DT5550 has to be connected to the computer through a specific programmer cable. The list of the supported programmer cables is provided by Xilinx, can be found in the UG908 “Vivado Design Suite User Guide, Programming and Debugging” and it is reported here:
- Xilinx® SmartLynq Data Cable (HW-SMARTLYNQ-G)
- Xilinx Platform Cable USB II (DLC10)
- Xilinx Platform Cable USB (DLC9G, DLC9LP, DLC9)
- Digilent JTAG-HS1
- Digilent JTAG-HS2
- Digilent JTAG-HS3
- Digilent JTAG-SMT1
- Digilent JTAG-SMT2
Then the “Program FPGA” button in the “Compiler” group of the “Home” toolbar can be clicked to start the DT5550 FPGA programming process. The “Compiler Output” is automatically displayed, the progress bar on the right corner of the status bar starts to indicate the progression of the programming process, while the status bar on the left corner of the status bar changes from “IDLE” to “PROGRAMMING”. The SCI-Compiler generates a .tcl file in the “HDL” folder of the current project to execute from the shell the Vivado software. In this file it is specified the .bit file that has to be used to program the FPGA, which is automatically taken from the “output” folder of the project currently opened in the SCI-Compiler. As a result, in order to program an FPGA with a specific bitstream, the correspondent project has to be opened with the SCI-Compiler. Then the Vivado process is executed and in the “Compiler Output” the redirected Vivado output is shown. First, Vivado opens the available programmer cables, connects to them and opens the correspondent FPGA. Then Vivado programs the FPGA with the bitstream file and when the process is terminated, if no error occurred, the “Target device programmed successfully!” message is displayed. Otherwise, the process is terminated and an error message is reported in red to notify to the user the issue that occurs. In both cases, at the end of the process, the status bar returns to “IDLE” and the progression bar is reset to be prepared for a new process.
The V2495 can be programmed trough the supported programmer cable USB-Blaster, described in the UG-USB81204 “Intel FPGA USB Download Cable User Guide”. The SCI-Compiler automatically uses as firmware file the .sof file of the “output” folder of the currently opened project. As a result, in order to program an FPGA with a specific bitstream, the correspondent project has to be opened with the SCI-Compiler. The “Program FPGA” button in the “Compiler” group of the “Home” toolbar allows to start the FPGA programming process. The “Compiler Output” is automatically displayed to show the Quartus redirected output, the progress bar on the right corner of the status bar starts to indicate the progression of the programming process, while the status bar on the left corner of the status bar changes from “IDLE” to “PROGRAMMING”. First, Quartus is executed to list the available programmer cables, which will be shown in the “Compiler Output”. Then, if a USB-Blaster cable has been identified, automatically the firmware is downloaded to the correspondent FPGA. The “Target device programmed successfully!” message is displayed at the end of the process if no error occurred. In case of error, the process is terminated and a message is reported in red to indicate the issue to the user. In both cases, at the end of the process, the status bar returns to “IDLE” and the progression bar is reset to be prepared for a new process.
