IDE User Interface

Starting window

When the installation procedure has been completed, the user can run the program by clicking the correspondent icon. At the start the following “Starting” window appears to allows the user to create a new project, to open a recent project or to explore the example projects that have been provided with the program.

Create Project

The “Create Project” tab allows the user to create a new project. The user has to click one of the two icons to choose to create a project that has to be implemented on the V2495 or to the DT5550. Then, the name of the project can be specified in the “Project Name” field, while the folder in which the project will be saved has to be written in the “Project Folder” field. The “Browse…” button allows to choose the project folder by looking at the system tree. The “Create” button will then create a folder at the desired path with the same name of the project. Inside this folder the following files/folders will be created: a .scf file, the file format specific of the SCI-Compiler, containing all the information of the project, a .jpg image of the diagram (at the start it is empty), and three folders, “HDL”, “Library” and “Output”, that will be filled during the compilation process.

Open Recent

The “Open Recent” tab allows to open a project that the user has previously created and saved. The box on the left shows in chronological order the recent project files list. By clicking on a file, the image of the diagram contained in the project will be displayed on the right and the field in the bottom will show the .scf file path. By pressing the “Browse…” button it will be possible to choose a project file (with extension .scf) by searching through the computer folders. The “Open” button allows to open the selected project file and load the correspondent diagram in the “Diagram” section of the User Interface.

Examples

The “Examples” tab allows the user to create a project by starting from an available example provided with the program. The examples are pre-compiled projects files (.scf) that the user can open, explore using the “Help” tool and compile to obtain the compilation output file that can be uploaded on the board FPGA. The box on the left shows all the example folders organized by board type and category. By clicking on an item, the name of the project file will appear in the “Project Name” field, the image of the project diagram will be displayed on the right and the description of the example functionalities is reported below the image. Then, the user can set the folder in which the project will be created by writing the path in the “Create Project in folder” field or by using the “Browse” button. The user can also decide to change the project name by using the correspondent field. The “Create” button will create a project containing the blocks and the connections of the selected example with the name and the destination folder specified by the user.

Main Interface

When the user has chosen one of the three available options in order to create or open a project file, the main interface will be shown.

The main interface is organized as follows:

• “File Menu”: this menu allows to open a new or a recent project, to save the current project and to close the application;

• Toolbars: the “Home” toolbar contains the same functionalities of the “File Menu”, the controls needed to menage the operations of the “Diagram”, of the “Editor” and of the compilation, while the “Tools Box” toolbar contains the buttons to insert in the diagram all the blocks that can be implemented in the board FPGA;

• Resources and Settings: this section has two tabs; the “Project File” tab allows to manage the files of the project and to see a block information through the “Help”, while the “Hardware Settings” tab can be used to select the board connectors, clocks and registers settings to be configured;

• “Diagram”, “Editor” and “Compiler Output”: this section allows respectively to graphically design the FPGA firmware by exploiting and interconnecting the available blocks, to configure the board connectors, clocks and registers settings and to read the output messages of the compilation process;

• “Status”: this toolbar shows on the left the license information and the program status and on the right a bar to indicate the progression of the current process.

At the top of the window, next to “Nuclear Instruments SciFirmware Compiler” it will be displayed the name of the current project.

File Menu

The “File Menu” can be visualized by clicking the blue button in the Toolbars region. The “New” item shows, when clicked, the “Starting” window and allows to create a new project. The “Open” item enables the user to browse the computer files and to open an already created project file with the .scf extension. The “Save” item saves the current project and updates the .jpg image of the diagram and the .scf file. The “Save As” item gives the possibility to change the name of the current project and to save it in a different location. The “Exit” item closes the program.

Toolbars

Home Toolbar

The “Home” toolbar contains some controls that are organized in sub-groups dedicated to different types of actions.

The “File” sub-group contains the same buttons of the “File Menu”, with the same functionalities described above.

The “Tools” sub-group has controls that can be used with the blocks of the “Diagram”. The “Copy” button allows to keep in memory the selected blocks and wires, the “Cut” button removes the selected elements but keeps them in memory, the “Paste” button allows to paste the elements that have been stored with the “Copy” or the “Cut” buttons. The “Undo” button erases the last action performed in the “Diagram”, while the “Redo” button allows to perform again an action that has been undone.

The controls of the “Editor” sub-group are necessary to perform the operations in the “Editor” section. The “Add” and the “Add Multi” buttons can be used to add one or multiple user-defined clocks or registers, as explained afterwards. The “Delete” button can be used to remove a selected user-defined clock or register. The “Reload” resets the “Editor” section that is selected when the button is pressed.

The “Compiler” sub-group contains the controls related to the compilation procedure. The “Compile” button starts the compilation on the user computer: a .vhdl file is generated from of the user graphically designed firmware. A .tcl file is created and the Vivado or Quartus program, depending on the target board chosen for the project, will be executed from the shell. The output of the program execution is redirected to the “Compilation Output”. For more details, please see the Firmware Compilation. The “Program FPGA” button allows to program the board FPGA by using the bitstream file generated during the firmware compilation process, connecting the board to the computer with a specific programmer cable and calling the Vivado or Quartus from the shell. Also in this case the output of the process is redirected on the “Compiler Output”. For further details, please see the FPGA Programming paragraph. The “Settings” button allows to set the compilation configuration, as described in the Sci-Compiler Configuration paragraph, and to menage the license, as explained in the Sci-Compiler License section. The “Resource Explorer” button opens a window that allows to connect with one of the two supported board types and to test the FPGA firmware. The functionalities of the “Resource Explorer” will be explained in detail in the Resource Explorer paragraph.

Tools Box Toolbar

The “Tools Box” toolbar contains all the pre-compiled implemented blocks for the selected project board, divided in groups depending on their category. The content of the sub-menus of each group, i.e. the available blocks, depends on the board selected for the current project; in the Components paragraph it will be specified for each block the board it has been implemented for.

The “Wire” group contains all the single wire blocks, organized in sub-menus:

• the “Board Pin” allows to use the I/O board pins,
• the “Misc” contains constant values, boolean variables, clocks, and conversion between binary and decimal values,
• the “Binary Operations” allows to implement the main bitwise binary operations,
• the “Sub-design” enables to select a sub-design file and synchronize it in order to insert it in the main diagram file.

The “Logic” group contains the following sub-menus:

• the “Boolean Logic” allows to implement all the boolean logic basic operations,
• the “Sequential Logic” has edge detectors, latches and flip-flops,
• the “Timer Counters” contains scalers, chronometers, timers, counters and frequency meters,
• the “Comparator” has blocks that can be used to compare signals,
• the “Mux” allows to implement multiplexer and de-multiplexer,
• the “Delay Memory” contains blocks to implement delays, serialization and deserialization, RAM, ROM, various type of buffers and a pattern generator tool.

The “Signal Processing” group comprises:

• the “State Machine” menu to implement a finite state machine,
• the “ALU” menu containing the basic ALU operations,
• the “Timing” menu with blocks implementing the Time to Digital Converter, the Single Channel Analyzer and the Time over Threshold,
• the “DAQ” menu which allows to implement the oscilloscope, the digitizer, the baseline restorer, the charge integration, the trapezoidal filtering, the trigger logic, the logic analyzer and the spectrum acquisition.

The “Communication” group is divided in the following sub-menus:

• the “Register” allows to read and write directly on the board register
• the “Serial Bus” offers the possibility to choose between the I2C, the SPI or the UART communication protocols.

The functionality of each block will be explained in detail in the Components section.

Resources and Settings

Project File

The “Project File” tab is organized in two sections.

The section on top shows the files contained in the project organized in a tree view:

• represents the main file project,
• denotes the sub-design file project.

By clicking on a file the correspondent content will be shown in the “Diagram” and the “Tools Box” toolbar will be displayed.

This button allows to create a new sub-design file.

This button deletes the selected sub-design file.

This buttons allow to synchronize a selected sub-design file in order to insert it as a block in the diagram of the main project.

The section on bottom displays the “Help”: by clicking on a block in the diagram, there will be shown the correspondent information explaining the block functionalities, as it is done in the Components section.

The “Help” reports the name of a block and its category, with arrows that allows to navigate the various sections. The “Help” shows

a label indicating if the block is available for a specific board ( or ), the image of the block and its description. This explanation is followed by a summary of all the input and output signals of the block, each one with the signal name, the label specifying the signal type (integer or logic vector ), the label indicating the signal direction (input or output ), the signal size and the signal brief description.

Diagram, Editor and Compiler Output

Diagram

The “Diagram” allows to graphically design the FPGA firmware. The “Diagram” section and the “Tools Box” toolbar will be displayed by clicking on the “Diagram” tab. On the tab it will appear also the name of the selected project file, as in the section it will be shown the diagram of the correspondent file. A block can be added to this kind of sheet by clicking the item of a sub-menu in the “Tools Box” toolbar. It can be linked to another block by connecting the circle identifying its output to the circle defining the input of the other block. The wire that is created corresponds to a signal: the arrow at one of the ends of the wire indicates the direction of the signal, while the number reported between square brackets along the wire represents the size of the signal. Two blocks can be connected only if the type (integer or vector) and the size of the output signal of one block matches the required features of the input signal of the other block. If the user is trying to link two blocks that can not be connected, an error message will be shown. In addition, the output of a block can have multiple connections, while the input of a block is allowed to have only one connection. If the main input and output (In and OUT of each block) will be left unconnected, an error will occur during the compilation and will be notified in the “Compiler Output” console. To the other input signal that are not specified it will be assigned a default value (es: the board Global Reset signal to the RESET input, the asynchronous clock signal for the CLK input).

In order to facilitate the design, some keyboard shortcuts are available and their description can be found in the Shortcuts section.

Project Settings

The project settings tab allows to define project information ad access to the board configuration.

If precompiled cores is Enable the compilation of the process will be speed up but only a small portion of source code is released open source to the user. The main modules is pre-compiled on Vivado 2017.4 and dcp file is provided as closed ip core.

Board Configuration

If in the “I/O Config” the item “Bank Connector” is selected, in the “Editor” section the list of all the I/O will be shown. The following window reports the result in the case in which the board selected for the project is the DT5550. All the 48 digital I/O can be configured to be input or output and can became LVDS if the correspondent checkbox is flagged. In addition, the signal on each connector could be inverted by flagging the correspondent checkbox. The configured input and output will then become available in the correspondent blocks in the “Board Pin” menu of the “Tools Box” toolbar in order to be added in the diagram.

The following window reports the result in the case in which the board selected for the project is the V2495. The “a” and “b” connectors could only be used as input, the “c” connectors are available only as output, while the “d”, “e” and “f” connectors could be configured either as input or output. The signal on each connector could be inverted if the correspondent checkbox is flagged.

The following are the pin settings for the DT5550W Petiroc. The direction of all pin is fixed and is not possible to select between single ended and differential

in board configuration it is possible to enable/disable the clock to the ASIC in order to reduce the noise in Photon Counting/ Analog readout applications

Compiler Output

The “Compiler Output” section is displayed automatically if the “Compile” or the “Program FPGA” buttons are pressed, but can also be visualized by clicking the “Compiler Output” tab. Here the massages of the various operation occurring while the software is running are reported to the user. The messages describing the operations executed by the SCI-Compiler itself, as the creation of a new project folder, the opening of a project, the creation of all the files and folders necessary for the firmware compilation, are displayed in blue. The output of the Vivado or Quartus process that are redirected in this console are visualized in black. In addition, all the warning massages are displayed in orange, while all the error messages are reported in red.

Status

The bar on the bottom of the software graphical interface is composed by three elements:

• the status label on the left corner of the status bar indicates the process that is executed by the software: it is “COMPILING” if the compilation process is in execution, “PROGRAMMING” if the FPGA programming process is running and it is “IDLE” if there is no Vivado or Quartus process in execution;
• the progress bar on the right corner of the status bar shows the progression of the current process (the firmware compilation or the FPGA programming);
• the license label shows the information related to the license, which is provided through the USB flash drive. In particular it will be displayed the license number and the maximum software version supported by the license. If there are problems with the license validity an error message will be shown. For more information on the license, please see the Sci-Compiler License paragraph.