Hardware setup and firmware design
This is the basic tutorial about DT5550W Citiroc asic configuration, HV control in Photon Counting application.
In this application we will implement a rate meters measuring the signal rate on all the Citiroc Trigger Outputs
For the experiment we need:
- DT5550W Citiroc
- SiPM matrix(Hamamatsu S13361-3050AE-08)
- Dark box (provided with DT5550W kit)
- light pulser (CAEN SP5601)
- Optical Fiber
This is a picture of the setup:
The light from the light pulser is captured by the SiPM under the dark box. The light collected triggers the Asic. Counters inside the FPGA counts the number of transitions of each trigger I/O of the Asic
In order to be able to perform this experiment we have to:
- Configure the Asic
- Configure the high voltage generator on the board
- Multi channel rate meter to measure the trigger rate in output from Citiroc Trigger module
The following Sci-Compiler project implements the functionalities above. All WeeROC Asic virtual blocks can be found in the board menu
Sci-Compiler include in the DT5550W examples this project under name Citiroc Step By Step
The Configuration for the Citiroc is performed by the Petiroc Slow Control block, It is possible to chose the asic to configure, the default configuration (configuration performed at boot) and the default monitor configuration. The Slow Control block is memory mapped block. It means that it is possible to access via USB (using the SDK or the Resource Explorer) in order to customize the parameters.
Each processing channel is designed to count the transition of on of the trigger output. When a trigger make a 0→1 transition the counter internal to the rate meter increment by one.
The rate meter update the rate register every second if 160MHz reference clock is selected
The rate meter is automatically mapped on USB as rate meter device. SDK function are embedded in the library in order to implement the rate measurement
The memory manage tab allows the user to select the appropriate address for each block in the design
Address can be manually defined entering it in PHY Hex Column or automatically defined pressing the Auto Assign Button. A defined address can be locked checking Manual Assigned checkbox this will prevent auto assign to override that particular address
A Json file with address / peripheral mapping is automatically generated compiling the project. The file will be store in the library folder inside the project folder.
Start compiling pressing Start compiler button. It will took from 10 to 20 minutes. At the end of compilation, if everything is successful, the bitstream will be generated.
Connect the board with USB3 and the JTAG USB port (see DT5550W documentation), power on the board and press Program FPGA from Sci-Compiler Top menu.
The firmware will be loaded on the board
Testing
We will use the Resource Explorer tool in oder to perform a small test of the functionality of the design. Rescource Explorer is a small tool included in Sci-Compiler that allows the users to interact with the firmware without write any line of code.
Open Resource Explorer from Sci-Compiler main menu
Select DT5550W-PETIROC in the board list. Press Scan for board and select the correct Serial Number in the list.
Verify the path of the JSON file corresponding to the project JSON path.
Connecting to the board all available memory mapped resource will be discovered by the Resource Explorer. We will detect CitirocCfg, HVControllerm and MCRateMeter (Multichannel Rate Meter)
We can first of all configure the high voltage: Right click on i2c_master_0 under HCcontrol → Open Configuration and set HV to 54 V and Enable it.
Pressing update button the Voltage Monitor will show the current HV Voltage, Current and SiPM sensor temperature
The configuration of the Citiroc Asic can be done from the CitirocCfg tool
The Generate button will invoke the Asic configuration tool. The tool will return to the Configuration Form the Asic bitstream. It is possible to copy and paste this bitstream in order to use it in the SDK function
Set the configuration as follow:
- Charge Threshold: 200
- Time Threshold: 300
- Polarity: Positive
- No latch on trigger
This is the bitstream generated for this example (can be copy and pasted in the Citiroc Configuration Tool)
1110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110111011101110110111111111111111111111111111111111111111111011110000111111101111001111011100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000000000111111110100101100010010110011111111111111011
Press Send to configure Asic
Open the RateMeter, select auto read and start
