Step by Step example for DT5550W Petiroc

Hardware setup and firmware design

This is the basic tutorial about DT5550W Petiroc Asic configuration, HV control for a  Photon Counting application.

For the experiment we need:

• DT5550W Petiroc,
• SiPM matrix(Hamamatsu S13361-3050AE-08)
• Dark box (provided with DT5550W kit)
• light pulser (CAEN SP5601)
• Optical Fiber

This is a picture of the setup:

The light from the light pulser is captured by the SiPM under the dark box. The light collected triggers the Asic. Counters inside the FPGA counts the number of transitions of each trigger I/O of the Asic

In order to be able to perform this experiment we have to:

• Configure the Asic
• Configure the high voltage generator on the board
• Counts the trigger and store in a register (one for each channels)

The following Sci-Compiler project implements the functionalities above. All WeeROC Asic virtual blocks can be found in the board menu

Sci-Compiler include in the DT5550W examples this project under name Petiroc Photon Counting

The Configuration for the Petiroc is performed by the Petiroc Slow Control block, It is possible to chose the asic to configure, the default configuration (configuration performed at boot) and the default monitor configuration. The Slow Control block is memory mapped block. It means that it is possible to access via USB (using the SDK or the Resource Explorer) in order to customize the parameters.

Pressing edit button the WeeROC configuration tools will open

Details on the configuration will be explained below.

Each processing channel is designed to count the transition of on of the trigger output. When a trigger make a 0→1 transition the counter increment by one.

Each register is mapped on USB on a particular address and can be read by SDK or Resource Explorer

The memory manage tab allows the user to select the appropriate address for each block in the design

Address can be manually defined entering it in PHY Hex Column or automatically defined pressing the Auto Assign Button. A defined address can be loked checking Manual Assigned checkbox this will prevent auto assign to override that particular address

A Json file with address / peripheral mapping is automatically generated compiling the project. The file will be store in the library folder inside the project folder.

Start compiling pressing Start compiler button. It will take between 10 and 20 minutes, depending on your machine performances. At the end of compilation, if everything is successful, the bitstream will be generated.

Connect the board with USB3 and the JTAG USB port (see DT5550W documentation), power on the board and press Program FPGA from Sci-Compiler Top menu.

The firmware will be loaded on the board

Testing

We will use the Resource Explorer tool in oder to perform a small test of the functionality of the design. Resource Explorer is a small tool included in Sci-Compiler that allows the users to interact with the firmware without write any line of code.

Open Resource Explorer from Sci-Compiler main menu

Select DT5550W-PETIROC in the board list. Press Scan for board and select the correct Serial Number in the list.

Verify the path of the JSON file corresponding to the project JSON path.

Connecting  to the board all available memory mapped resource will be discovered by the Resource Explorer. We will have registers (the 6 counters), Petiroc Configuration and HV Controller

We can first of all configure the high voltage: Right click on i2c_master_0 under HCcontrol → Open Configuration and set HV to 54 V and Enable it.

Pressing update button the Voltage Monitor will show the current HV Voltage, Current and SiPM sensor temperature

The configuration of the Petiroc Asic can be done from the PetirocCfg tool

The Generate button will invoke the Asic configuration tool. The tool will return to the Configuration Form the Asic bitstream. It is possible to copy and paste this bitstream in order to use it in the SDK function

Set the configuration as follow:

• Charge Threshold: 300   → Please note that in positive polarity as lower value of threshold field correspond to higher higher threshold !!! 
• Time Threshold: 200 → Please note that in positive polarity as lower value of threshold field correspond to higher higher threshold !!! 
• Polarity: Positive
• No latch on trigger

• disable charge or32
• disable time or2 (MUST BE DONE due to a silicon bug on the chip)

This is the bitstream generated for this example (can be copy and pasted in the Petiroc Configuration Tool)

0000000000000000000000000000000000000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100000001100010000000000000000000000000000000000000000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000010000011101001011000011001000110011110100000111111111101111111010011111111001111111111011000011

Press Send to configure Asic

Skip monitor configuration

Open C1 and C2 counter from register menu, set Auto Read Mode to 50ms and show number as decimal. Start both register readout

You will see that C2 counter will count photons (when light pulser is on) while C1 will receive just a small amount of light. The pixel are in different part of the matrix.