Field programmable gate arrays (FPGAs) are integrated circuits that enable designers to program customized digital logic in the field. FPGAs have been around since the 1980s and were originally conceived to give all design teams the ability to create custom logic. Compared to other ways of building hardware, FPGAs enable you to build exactly the hardware you need.
Modern FPGAs consist of mixes of configurable static random access memory (SRAM), high-speed input/output pins (I/Os), logic blocks, and routing. More specifically, an FPGA contains programmable logic elements called, naturally, logic elements (LEs), as well as a hierarchy of reconfigurable interconnections that allow the LEs to be physically connected to one another. You can configure LEs to do complex functions or to simply perform basic logic gates, such as AND and OR.
Today, hard intellectual property (IP) can be built into the FPGA fabric to provide rich functionality while reducing power and lowering cost. Some examples of the hard IP included in today’s FPGAs are memory blocks, calculating circuits, transceivers, protocol controllers, and even central processing units (CPUs).
The building blocks of an FPGA
You can build anything digital from three simple pieces: a wire, a logic gate, and a register. A register remembers a piece of information until it is told to remember something else. A logic gate performs simple logic operations on signals, and a wire connects these other pieces.
Logic gates
Logic gates perform the core functionality of digital circuits, which means they perform simple logic on inputs — electrical pulses that your computer uses to represent 0s and 1s (more on that later). On their own, these simple operations do not do much, but when you put thousands or even millions of these together you can do something really powerful. Your computer’s CPU is made up of billions of logic gates that allow your computer to do all the cool stuff that it does.
The basics of Boolean algebra operations are the following:
- And (conjunction) is denoted as x AND y, which yields a result of true if both x and y are true, and false otherwise.
- Or (disjunction) is denoted as x OR y, which yields true if either x or y is true, and false if neither x nor y is true.
- Not (negation) is denoted as NOT x, which yields true if x is false and false if x is true.
Registers
Registers are simple devices that store pieces of data to be used in the future. Think of registers as a short-term spot for placing data that you can access quickly. Registers keep whatever information is given to them until they are told to forget it and keep new information.
Wire
The third piece of all digital things is the wire used to connect all the registers and logic gates.
Hard IP
Hard IP is the intellectual property built into the FPGA, such as DRAM controllers, PCIe controllers, clock generators, and big blocks of memory. In fact, there is so much hard IP in today’s FPGAs that they really have become systems on chips (SoCs). Not only are common functions that most system designers need built into the hard IP of the FPGA, but even many less commonly needed functions like high-speed serial transceivers, and digital signal processor (DSP) multiplier-accumulators for signal processing can be included. Today, even dual-core ARM (ARM is a brand of microprocessor designs) CPU subsystems may be built in.
The core of an FPGA is simply an array of these logic gates and wires etched into an integrated circuit in a way that allows you to reconfigure them. So really, an FPGA, in its simplest form, is a big array of colorful rectangles placed on a rectangular table that can be arranged in the manner desired by its owner.
The fact that FPGAs are field programmable gives them an edge over ASICs because the same hardware can be reprogrammed in response to changes in design. If the design uses an ASIC, changing the design requires the hardware to be scrapped and new hardware has to be built to reflect the design changes. More designers are choosing FPGAs over ASICs for their designs. If you are thinking about using FPGAs in your designs, read on to find out more about the design flow for designing with FPGAs while taking full advantage of their embedded hardware.
Xilinx Kintex 7 Configurable Logic Blocks
In the configurable logic block of a Xilinx Kintex 7 FPGA (Slice) there are the following internal elements:
- Four 6 input Lookup table to implement any logic function
- A fast carry chain (red) to accelerate the carry propagation in addition
- Multiplexers
- Eight registers to store information and implement sequential logic
Classical FPGA design flow overview
FPGA engineering process usually involves the following stages:
- Architecture design. This stage involves the analysis of the project requirements, problem decomposition and functional simulation (if applicable). The output of this stage is a document which describes the future device architecture, structural blocks, their functions and interfaces.
- HDL design entry. The device is described in a formal hardware description language (HDL). The most common HDLs are VHDL and Verilog.
- Test environment design. This stage involves writing of test environments and behavioral models (when applicable). They are later used to ensure that the HDL description of a device is correct.
- Behavioral simulation. This is an important stage that checks HDL correctness by comparing outputs of the HDL model with the behavioral model (being put in the same conditions).
- Synthesis. This stage involves conversion of an HDL description to a so-called netlist which is basically a formally written digital circuit schematic. Synthesis is performed by a special software called synthesizer. For an HDL code that is correctly written and simulated, synthesis shouldn’t be any problem. However, synthesis can reveal some problems and potential errors that can’t be found using behavioral simulation, so, an FPGA engineer should pay attention to warnings produced by the synthesizer.
- Implementation. A synthesizer-generated netlist is mapped onto particular device’s internal structure. The main phase of the implementation stage is place and route or layout, which allocates FPGA resources (such as logic cells and connection wires). Then these configuration data are written to a special file by a program called bitstream generator.
- Timing analysis. During the timing analysis a special software checks whether the implemented design satisfies timing constraints (such as clock frequency) specified by the user.
While the design phases are tasks delegated to the system engineer, synthesis and implementation phases are automatically performed by the FPGA manufacturer programming software.