Sci-Compiler Design Flow

Sci-Compiler is an automatic code generator software that starts from a graphical block diagram to generate a VHDL peace of code that implements the required functionalities.

Sci-Compiler uses a prebuilt library set containing macro-blocks with complex functionalities. Each macro-block could be imagined as a modular instrument (MCA, Oscilloscope, Digitizer, TDC) that the user could connect with other macro-blocks.

Programming with Sci-Compiler is much more similar to implement an experimental setup then developing a software.

• 1^st step: user places the macro-functional blocks and connects them together.
• 2^nd step: Sci-Compiler generates the VHDL code starting from the user design.
• 3^rd step: Sci-Compiler executes Xilinx Vivado or Intel Quartus in background in order to compile the firmware and generate the bitstream.
• 4^th step: Sci-Compiler converts the bitstream in the proper configuration file compatible with one of the supported platform (DT5550, V2495).
• 5^th step: Sci-Compiler downloads the bitstream on the target hardware platform.
• 6^th step: Sci-Compiler generates a C library and an example project (that could be compiled in VC++, gcc, XCODE) in order to test the communication bus.

Sci-Compiler produces in output:

• a configuration file for the target hardware;
• an FPGA project in VHDL;
• a series of C files that could be compiled to interface with the hardware using USB/VME/Ethernet bus.

Why do I need to install Xilinx Vivado / Intel Quatus in order to compile a project?

FPGA manufacturer spends million dollars in order to develop a software to convert (compile) the VHDL into a FPGA configuration file. Synthesis, mapping, place and route are extremely complex operations and only the same FPGA manufacturer can efficiently develop having a deep (and secret) knowledge of the internal structure of their integrated chip. Sci-Compiler is a code generator, not an FPGA compiler. Sci-Compiler generates VHDL and Verilog code that a FPGA manufacturer tool can compile into a working FPGA configuration file. Sci-Compiler is also able to generate Vivado and Quartus project files, execute them in background and intercept messages in its console. For the user, Sci-Compiler is a fully integrated IDE: pressing the compile button the tool generates files and projects, executes the FPGA compiling tool, gets the output file, programs the connected target and generates communication libraries.