IEEE NSS MIC RTSD 2025 Conference.

The NUSES Space Mission Readout Architecture Using New FPGA Technology

The NUSES mission features two payloads: Ziré for cosmic/gamma rays and space weather, and Terzina for atmospheric Cherenkov light and UHECRs. A modular readout handles >1800 SiPM channels using Citiroc ASICs, low-power FPGAs, and Zynq Ultrascale+ SoCs with onboard neural network inference. This design combines density, power efficiency, and resilience for advanced space missions.

Design and Implementation of the ASTRI Camera Cherenkov Telescopes Readout and Control Electronics

The ASTRI telescope features a novel readout and control system built on Zynq UltraScale+ SoC, managing both DAQ and slow control for 37 PDMs (64 SiPM channels each). White Rabbit provides 1 ns timing; data are transmitted at 1 Gbps TCP/IP. The distributed OPC-UA slow control covers configuration, calibration, mechanics, and thermal regulation. The architecture ensures robustness for Cherenkov astronomy.

Sci-Compiler: Advancing FPGA-Based DAQ for Ultra-Fast Digitizers

The latest generation of ultra-fast digitizers is pushing the limits of FPGA-based data acquisition (DAQ) architectures. New platforms such as the CAEN V2730 (32 channels, 14-bit at 500 MSPS), V2751 (16 channels, 16-bit at 1 GSPS), and the Nuclear Instruments DAQ121/DAQ141 (32 channels, 12/14-bit at 1 GSPS), together with the DT9000 (8 channels, 14-bit at 5 GSPS), demand a new approach to real-time signal processing.

Traditional FPGA designs cannot directly sustain event reconstruction at sampling rates of 1–5 GSPS. To address this challenge, Sci-Compiler has been re-engineered to support time-multiplexed signal processing, transforming a single GHz data stream into multiple parallel buses running at lower frequencies. This required the redesign of digital energy filters, CFDs, and trigger logic to operate seamlessly on interleaved data streams.

Sci-Compiler abstracts this complexity through its graphical design interface and modular IP library, enabling flexibility, scalability, and rapid reconfiguration for next-generation experiments.

Interleaved SAR 20-bit ADC Architecture for Direct Sampling in X-ray Spectroscopy

We developed a DSP technique for SDDs using a 20-bit SAR ADC with four interleaved channels (160 MSPS). A Zynq SoC handles phase alignment, calibration, trapezoidal filtering, and PC interfacing. Tests with ARDESIA SDD show FWHM 128 eV at 2 µs shaping and 140 eV at 1 Mcps, outperforming analog approaches.

Development of Super-MuSR’s 960 Channel SiPM Detector Barrel

Super-MuSR, under construction at ISIS (UK), will complete in 2027. It uses two barrels of 480 SiPM channels each inside a 0.65 T Helmholtz coil. The system features optimized scintillator + WLS fiber geometry, ESR reflectors, 1920 Hamamatsu S13360-1325 SiPMs, and per-channel biasing for gain matching. Results from the first assembled barrel staves will be shown, covering signal characteristics, stability, EMI isolation, and design optimizations.

Real-Time Active Collimation of Charge-Sharing Events in Monolithic SDD Arrays

Monolithic SDD arrays suffer from charge sharing. We implemented real-time active collimation on a CAEN DT5560-based DPP, integrating the CASPER algorithm and its AI variant for on-line CS recovery without sacrificing area.

Real-Time Pile-Up Discrimination in Muon Detectors via Embedded Deep Learning

A CNN was trained for pile-up discrimination in muon detectors at Gcps rates. Embedded inference on Jetson Orin Nano and FPGA (via hls4ml) achieved low-latency online processing, enabling autonomous pile-up resilient readout.

Characterization of an ASIC-based Readout System for the SAND Experiment

For DUNE’s SAND calorimeter, a Radioroc ASIC + FERS picoTDC approach extends dynamic range: ADC best for >100 mV signals, ToT best for small signals. Results validate the ASIC-based FERS solution for high-density neutrino detectors.

Accelerating the Design of Readout Systems for New Physics Experiments Using FPGA Visual Programming

We present a visual programming ecosystem for FPGA DAQ design: Sci-Compiler. By connecting functional blocks (scalers, TDCs, PSD, energy filters), users build custom pipelines without HDL expertise. It supports a wide range of open FPGA boards, from single-channel to 128 channels at up to 5 GSPS, accelerating prototyping for nuclear physics experiments.