IEEE NSS MIC RTSD 2026 Conference.

FPGA-Based Real-Time SiPM Emulator with Sub-Nanosecond Temporal Quantization

This work presents a real-time FPGA-based Silicon Photomultiplier (SiPM) detector emulator capable of reproducing physically accurate detector waveforms at 16-bit resolution and 2.5 GS/s analog output rate. The proposed architecture combines microscopic event simulation with a temporally quantized event-streaming model, enabling real-time waveform synthesis directly inside FPGA logic while drastically reducing bandwidth requirements compared to traditional waveform streaming approaches. The emulator separates event generation from signal shaping: software layers generate timestamped photon-hit sequences derived either from analytical distributions, Geant4 simulations, or SimSiPM microscopic detector models, while the FPGA reconstructs the analog waveform through parallel Infinite Impulse Response (IIR) filter banks implementing the SiPM transfer function; a look-ahead recursive transformation enables II = 1 operation across all banks at 156.25 MHz, consuming approximately 235 DSP48E2 slices. A multi-phase temporal quantization architecture provides 0.8 ns effective timing precision using a 156.25 MHz fabric clock and eight temporal sub-phases. Experimental validation demonstrates excellent agreement between hardware-generated waveforms and analytical as well as SimSiPM-generated references, including pile-up scenarios with overlapping scintillation events reproduced through linear superposition. The prototype operates with an end-to-end latency of approximately 83 ns.

High-Rate FPGA-Based Fully Digital SiPM Readout for Photon-Number-Resolving Measurements in Quantum Optics and Quantum Communications

Photon-number-resolving (PNR) detection based on Silicon Photomultipliers (SiPMs) is emerging as a promising approach for high-rate quantum optics and quantum communication experiments, particularly for the possible implementation of hybrid schemes. We present a fully digital SiPM readout platform combining a 14-bit, 1 GS/s waveform digitizer with a real-time FPGA-based signal-processing chain optimized for fast charge extraction and photon-number reconstruction. The system is implemented on an open-FPGA architecture programmable through the Sci-Compiler framework, enabling custom firmware development without dedicated HDL design.

The firmware performs real-time baseline restoration, digital pole-zero compensation, synchronous triggering, and charge integration entirely inside the FPGA pipeline at full sampling rate. The system supports synchronous operation with externally or internally triggered laser sources and enables deterministic acquisition windows with nanosecond-scale integration gates.

Different Hamamatsu SiPM models were characterized using coherent and twin-beam optical states to evaluate the impact of detector gain, pixel pitch, pile-up, and photon detection efficiency on photon-number reconstruction. Measurements demonstrate reliable operation from mean photon numbers well below 1 up to more than 50 detected photons per pulse at repetition rates up to 1 MHz, with operation extendable toward 10–20 MHz depending on the analog front-end configuration. The digital processing chain significantly improves peak separation, dynamic range, and noise performance compared with conventional boxcar-based acquisition systems.

The presented architecture demonstrates how modern FPGA-based real-time digital processing can transform SiPM detectors into scalable, high-speed PNR systems suitable for next-generation quantum optics instrumentation and quantum communication protocols.

Sci-Compiler: Towards Cross-Platform FPGA Development and Automated CI/CD Workflows for Scientific Data Acquisition

Sci-Compiler is a graphical FPGA development environment for custom digital signal processing and data acquisition in nuclear physics, radiation detection, and scientific instrumentation. This contribution presents a major evolution of the platform, including the highly anticipated introduction of Linux support and automated firmware compilation through CI/CD pipelines.

The new alpha release for Linux represents a significant milestone, addressing a long-standing requirement from the scientific community and enabling Sci-Compiler to operate natively in Linux-based research environments. Together with newly introduced pipeline licenses, it opens the way to automated FPGA compilation, integration with Git-based workflows, reproducible firmware builds, and continuous validation of scientific instrumentation firmware.

The signal processing library has been substantially expanded with advanced FFT/IFFT architectures, real-time frequency-domain filtering, programmable FIR and CIC filters, digital modulation, waveform averaging, statistical analysis, and configurable signal generators. Extensive support for time-multiplexed processing enables efficient implementation of multichannel algorithms for high-sampling-rate digitizers.

Detector-oriented developments include improved trapezoidal processing for high-count-rate spectroscopy, pile-up rejection, rise-time discrimination, and flexible event packet generation. Extended simulation capabilities allow acquisition chains to be tested and waveforms, spectra, and event streams to be exported without physical hardware.

A redesigned graphical editor further improves productivity through intelligent signal connections, searchable processing blocks, hierarchical design tools, and integrated documentation.

These advances mark a transition towards an accessible, cross-platform and automated FPGA development ecosystem for modern scientific experiments.

TD-Link: A Daisy-Chain Optical Architecture for Integrated Data Readout and Deterministic Timing Distribution in Large-Scale Detector Systems

TD-Link is a versatile optical communication architecture combining high-throughput data readout and sub-nanosecond timing synchronization over a single optical fiber for large-scale detector systems. The protocol adopts a multidrop daisy-chain ring topology connecting one Data Concentrator to up to sixteen FERS front-end boards per link, with multiple independent links per concentrator, enabling scalable instrumentation with reduced optical infrastructure. Operating at 3.25 Gb/s, TD-Link transports data, synchronization, and control traffic within the same serial stream through a token-based protocol minimizing per-hop latency and supporting packet fragmentation.

The synchronization system distributes a global time reference (T0) with deterministic latency. On the concentrator, transmitter lane alignment exploits the half-full condition of the transceiver elastic buffer as a 1-bit phase detector. A firmware state machine iteratively adjusts the TX phase interpolator until the write-to-read pointer difference reaches half the buffer depth, locking the lane to a deterministic phase condition. A Digital Dual Mixer Time Difference (DDMTD) circuit is used only for inter-concentrator synchronization, compensating the phase offset between the recovered transceiver clock and the FPGA fabric reference clock.

On FERS boards, recovered clocks are cleaned through an external zero-delay PLL and retransmitted downstream, preserving phase coherence along the daisy chain. Deterministic T0 latency is ensured by disabling elastic buffers and routing timing signals through calibrated delay paths.

Experimental validation with CERN PicoTDC-equipped FERS boards demonstrates a synchronization sigma of 6 ps for boards sharing the same coaxial clock reference and below 25 ps for boards connected to different concentrators. The performance remains stable across repeated power cycles, confirming the robustness of the phase alignment strategy.

FPGA-Based Real-Time SiPM Emulator with Sub-Nanosecond Temporal Quantization

Poster presentation of the lightning talk above: a real-time FPGA-based SiPM detector emulator reproducing physically accurate detector waveforms at 16-bit resolution and 2.5 GS/s analog output rate, with 0.8 ns effective timing precision obtained through a multi-phase temporal quantization architecture and an end-to-end latency of approximately 83 ns.

Pile-Up Resilient X-Ray Spectroscopy via Direct Sampling and Waveform Fitting in SDDs

A fully digital readout architecture is described for high-throughput X-ray spectroscopy with silicon drift detectors (SDDs). The core challenge is the large-amplitude voltage ramp produced by transistor reset preamplifiers, which conventionally prevents direct digitization at spectroscopic resolution. In this work, sampling the preamplifier output with a 20-bit SAR ADC achieves a dynamic range exceeding 10⁶, eliminating any analog conditioning stage upstream of the digitizer.

Throughput is sustained by combining four converters in a time-interleaved scheme, yielding an aggregate sampling rate of 160 Msps. A Zynq SoC provides the processing backbone, performing inter-channel timing alignment, gain equalization, and concurrent execution of the signal processing pipelines.

Two energy estimation algorithms run in parallel on the digitised data: a ramp-corrected trapezoidal filter and a model-based least-squares fitter that uses linear regression over the full inter-event sample record, remaining accurate even when pulse separation shrinks to sub-microsecond intervals. Experimental characterisation with ARDESIA multi-pixel SDD arrays and KETEK single-pixel detectors yields an energy resolution of 120.7 eV FWHM at low rate, 150 eV at 1 Mcps, and 180 eV at 2 Mcps, with live time exceeding 90% throughout.

Towards a 64-Channel Monolithic SDD X-Ray Spectrometer for High-Throughput Synchrotron Applications

The increasing brilliance of fourth-generation synchrotron sources drives a growing demand for energy-dispersive X-ray fluorescence (XRF) spectrometers capable of handling extreme photon fluxes.

We present the design and characterization of the ARDESIA-64 instrument, a complete X-ray fluorescence (XRF) spectrometer for high-throughput synchrotron applications. The instrument integrates a highly scaled 64-channel monolithic Silicon Drift Detector (SDD) array, featuring a pixel pitch of 2.5 mm, within a compact, vacuum-compatible mechanical housing tailored for beamline integration.

At the conference, we will present the instrument design and comprehensive spectroscopic characterization results. The collimated 450 μm-thick sensor variant demonstrates an excellent average energy resolution of 125.9 eV FWHM at 5.9 keV. Preliminary high-rate tests confirm exceptional throughput capabilities, sustaining Input Count Rates (ICR) exceeding 800 kcps per channel while preserving an energy resolution of ~150 eV. The readout is performed by a 64-channel Digital Pulse Processor (DPP) based on the CAEN DT5560SE digitizer with firmware specifically adapted for high-throughput X-ray spectroscopy in synchrotrons.

Utilisation of the ISIS Digital Data Pipeline for Afterpulsing Analysis of PMT & SiPM Signals

This paper reports on the recently deployed ISIS Digital Data Pipeline, which has facilitated an in-depth examination of the detector signals coming from the suite of Muon Spectrometers. Signal processing and event-mode analysis has been used to understand the afterpulsing characteristics of three types of photosensor: the Hamamatsu R5505 1-inch PMT, the EMI-9954 2-inch PMT and the Hamamatsu S13360-1325PE SiPM. The R5505 was found to produce significant afterpulsing that can be identified via pulse shape discrimination due to their characteristically shorter fall time. This indicates impurity ionization, as the signals are not convolved with the scintillation response. The data pipeline has been tuned to suppress the afterpulses, producing data sets without this background contribution.