Case-Study
Case-Study, Integration, Design Flow
Bringing an existing VHDL code base into a graphical design
Most groups that would benefit from a graphical FPGA design tool already have VHDL. Often quite a lot of it: a detector interface written for a previous experiment, a serial protocol nobody wants to re-derive, a filter that took two people three months to get right, an algorithm that is the group’s actual intellectual contribution.
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