Filter cs: Design Flow

Card Image Case-Study Case-Study, Integration, Design Flow Case-Study VHDL Custom HDL GHDL Integration Legacy

Bringing an existing VHDL code base into a graphical design

Most groups that would benefit from a graphical FPGA design tool already have VHDL. Often quite a lot of it: a detector interface written for a previous experiment, a serial protocol nobody wants to re-derive, a filter that took two people three months to get right, an algorithm that is the group’s actual intellectual contribution.

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Card Image Case-Study Case-Study, Multi Channels, Design Flow, DSP Case-Study TM Time Multiplexing X2730 500 MS/S Concepts

Time multiplexing: what a TM signal is and what a lane means

Every block in the Sci-Compiler library now exists in two versions, and the second one is marked TM. Understanding what that means takes about ten minutes and saves a great deal of confusion, because TM is one mechanism that solves two quite different problems, and the mechanism cannot tell you which of the two you are using it for.

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